Split-row: A reduced complexity, high throughput LDPC decoder architecture

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 320-325

  Mohsenin, T ^a   Baas, B M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; CODE LENGTHS; COMPUTER DESIGNS; DECODING ITERATIONS; ERROR PERFORMANCES; GAUSSIAN CHANNELS; HIGH THROUGHPUTS; INTERCONNECT COMPLEXITY; INTERNATIONAL CONFERENCES; LDPC CODING; LDPC DECODERS; LDPC DECODING; LOWER ENERGIES; MIN-SUM; MIN-SUM ALGORITHMS; PARALLEL DECODERS; REDUCED-COMPLEXITY; ROW DECODER; ROW PROCESSORS; SIMULATION RESULTS; SUM-PRODUCT DECODING; WIRE LENGTHS;

CHLORINE COMPOUNDS; CODES (STANDARDS); CODES (SYMBOLS); ELECTRON BEAM LITHOGRAPHY; ENERGY DISSIPATION; FOOD ADDITIVES; ITERATIVE DECODING; PARALLEL ALGORITHMS; SIGNAL ENCODING; THROUGHPUT; VLSI CIRCUITS; WIRE;

DECODING;

EID: 49749151038     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380835     Document Type: Conference Paper

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