A memory efficient serial LDPC decoder architecture

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn V, Issue , 2005, Pages

  Prabhakar, Abhiram ^a   Narayanan, Krishna ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

LDPC decoder; Memory efficient decoding; Serial hardware decoder; SPA

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CACHE MEMORY; COMPUTER SIMULATION; CONSTRAINT THEORY;

LDPC DECODERS; MEMORY EFFICIENT DECODING; SERIAL HARDWARE DECODER; SPA;

DECODING;

EID: 33646811211     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2005.1416235     Document Type: Conference Paper

References (11)

1. C. Jones, E. Valles, M. Smith, J. Villasenor. Approximate-Min Constraint Node Updating for LDPC code design. IEEE conference on Military Communications, 2003. MILCOM 2003, 13-16 Oct 2003, pages:57-162.
2. F. Guilloud, E. Boutillon, J.L. Danger. A-Min Decoding Algorithm of Regular and Irregular Codes. Proceedings of the 3nd International Symposium on Turbo Codes & Related Topics,Brest,France, Sept 2003.
3. S. Sivakumar. VLSI Implementation of Encoder and Decoder for Low Density parity check codes. Masters Thesis,Texas A&M University,December 2001.
4. M.M. Mansour, N.R. Shanbhag. Memory efficient turbo decoder architecture for LDPC codes. IEEE workshop on Signal Processing Systems, 2002(SIPS'02), 16-18 Oct 02, pages: 159-164.
5. H. Sankar, K. R. Narayanan. Memory-Efficient Sum-Product Decoding of LDPC Codes. To appear in IEEE Tansactions on Communications.
6. E. Yeo, P. Pakzad, B. Nikolic, V. Anantharaman. High throughput Low-Density Parity-Check decoder architectures. IEEE Global Telecommunication Conference,2001. GLOBECOM'01, vol:5, pages:3019-3024.
7. T. Zhang, K.K. Parhi. A 54 MBPS (3,6)-regular FPGA LDPC decoder. IEEE Proc. of SIPS, pp. 127-132, 2002.
8. A. Selvarathinam, G. Choi, K. Narayanan, A. Prabhakar, E. Kim. A massively scalable architecture for low-density parity-check codes. Circuits and Systems 2003, ISCAS' 03, Volume 2, 25-28 May 2003. Pages:II-61-II64 vol.2.
9. K. Gunnam, G. Choi, M. Yeary. An LDPC decoding shedule for memory access reduction. Acoustics, Speech, and Signal Processing, 2004. ICASSP 04, vol:5, 17-21 May 2004, pages: 173-176.
10. Y Chen, D.Hocevar. A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder. IEEE Global Telecommunciations Conference, 2003. GLOBECOM'03, vol:1, 1-5 Dec.2003, pages: 113-117.
11. F. Zarkeshvari, A.H. Banihashemi. On implementation of min-sum algorithm for decoding low-density parity-check(LDPC) codes. IEEE Global Telecommunications Conference,2002. GLOBECOM'02, vol:2, Nov 17-21, 2002, pages: 1349-1353.