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Volumn , Issue , 2007, Pages 3740-3743

New power gating structure with low voltage fluctuations by bulk controller in transition mode

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; GAIN CONTROL; GATES (TRANSISTOR); TRANSISTORS;

EID: 34548858983     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378656     Document Type: Conference Paper
Times cited : (13)

References (9)
  • 2
    • 0034230287 scopus 로고    scopus 로고
    • Dual-threshold voltage techniques for low-power digital circuits
    • July
    • J. T. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," IEEE Journal of Solid-state circuits, 35(7):1009-1018, July 2000.
    • (2000) IEEE Journal of Solid-state circuits , vol.35 , Issue.7 , pp. 1009-1018
    • Kao, J.T.1    Chandrakasan, A.P.2
  • 6
    • 0034293891 scopus 로고    scopus 로고
    • A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere standby current
    • Oct
    • H. Kawaguchi, K. Nose, and T. Sakura, "A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere standby current,' IEEE Journal of Solid-State Circuits, vol. SC-35, pp. 1498-1501, Oct. 2000.
    • (2000) IEEE Journal of Solid-State Circuits , vol.SC-35 , pp. 1498-1501
    • Kawaguchi, H.1    Nose, K.2    Sakura, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.