Models and formal verification of multiprocessor system-on-chips

Journal of Logic and Algebraic Programming

Volumn 77, Issue 1-2, 2008, Pages 1-19

  Brekling, Aske ^a   Hansen, Michael R ^a   Madsen, Jan ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

Multiprocessor system on chips; Schedulability; Timed Automata; uppaal; Verification

Indexed keywords

AUTOMATA THEORY; CHLORINE COMPOUNDS; MICROPROCESSOR CHIPS; MODEL CHECKING; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS;

APPLICATION LEVEL; COMPUTATION TREE; COMPUTATIONAL MODELLING; DISCRETE MODELING; FORMAL ANALYSIS; FORMAL VERIFICATIONS; MULTI-PROCESSOR PLATFORMS; MULTI-PROCESSOR SYSTEMS; MULTIPROCESSOR SYSTEM-ON-CHIPS; PHONE APPLICATIONS; PROCESSING ELEMENTS; SCHEDULABILITY; SMALL SYSTEMS; SYSTEM VERIFICATIONS; TASK GRAPHS; TIMED AUTOMATA; UPPAAL; VERIFICATION; WORST-CASE EXECUTION TIMES;

TELEPHONE SYSTEMS;

EID: 49349083845     PISSN: 15678326     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jlap.2008.05.002     Document Type: Article

References (31)

1. Abdeddaïm Y., Asarin E., and Maler O. Scheduling with timed automata. Theoret. Comput. Sci. 354 2 (2006) 272-300
2. Abdeddaïm Y., and Maler O. Job-shop scheduling using timed automata. Proceedings of the 13th International Conference on Computer Aided Verification (CAV'01) vol. 2102 (2001), Springer
3. Alur R., and Dill D.L. A theory of timed automata. Theoret. Comput. Sci. 126 2 (1994) 183-235
4. Amnell T., Fersman E., Mokrushin L., Pettersson P., and Yi W. Times - A tool for modelling and implementation of embedded systems. Lecture Notes in Comput. Sci. 2280 (2002) 460-464
5. Behrmann G., David A., and Larsen K.G. A tutorial on uppaal. Lecture Notes in Comput. Sci. 3185 (2004) 200-236
6. Fersman E., Pettersson P., and Yi W. Timed automata with asynchronous processes: schedulability and decidability. Lecture Notes in Comput. Sci. 2280 (2002) 67-82
7. Graham R.L. Bounds on multiprocessor timing anomalies. SIAM J. Appl. Math. 17 2 (1969) 416-429
8. Halkjaer L., Haervi K., and Ingolfsdottir A. Verification of the LegOS scheduler using uppaal. Electron. Notes Theor. Comput. Sci. 39 3 (2000) 273-292
9. P. Hastrono, S. Klaus, S.A. Huss, An integrated SystemC framework for real-time scheduling assessments on system level, in: Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS'04), 2004.
10. Haubelt C., Falk J., Keinert J., Schlichter T., Streubühr M., Deyhle A., Hadert A., and Teich J. A SystemC-based design methodology for digital signal processing systems. EURASIP J. Embedded Syst. 2007 1 (2007) 15
11. F. Hessel, V.M. da Rosa, I.M. Reis, R. Planner, C.A.M. Marcon, A.A. Susin, Abstract RTOS modeling for embedded systems, Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), IEEE Computer Society, Washington, DC, USA, 2004.
12. Holzmann G.J. The SPIN Model Checker: Primer and Reference Manual (2003), Addison-Wesley
13. Kempf T., Doerper M., Leupers R., Ascheid G., Meyr H., Kogel T., and Vanthournout B. A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms. Proceedings of the Conference on Design, Automation and Test in Europe (DATE'05) vol. 2 (2005), IEEE Computer Society, Washington, DC, USA
14. V. Kianzad, S.S. Bhattacharyya, CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems, in: Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04), 2004.
15. Larsen K.G., Pettersson P., and Yi W. Uppaal in a nutshell. Int. J. Software Tools Technol. Transf. 1 1-2 (1997) 134-152
16. Liao T.G.S., Martin G., and Swan S. System Design with systemC (2002), Springer
17. M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, R. Zafalon, Analyzing on-chip communication in a MPSoC environment, in: Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04), IEEE, 2004.
18. J. Madsen, M.R. Hansen, K.S. Knudsen, J.E. Nielsen, A.W. Brekling, System-level verification of multi-core embedded systems using timed-automata, in: Proceedings of the 17th World Congress International Federation of Automatic Control Seoul, Korea, July 6-11, 2008, pp. 9302-9307.
19. Madsen J., Mahadevan S., and Virk K. Network-centric system-level model for multiprocessor SoC simulation. Interconnect-Centric Design for Advanced SoC and NoC (2004), Kluwer Academic 341-365
20. J. Madsen, K. Virk, M.J. Gonzalez, A SystemC-based abstract real-time operating system model for multiprocessor system-on-chip, in: Multiprocessor System-on-Chip, Morgan Kaufmann, 2004, pp. 283-312.
21. Mahadevan S., Virk K., and Madsen J. ARTS: a SystemC-based framework for multiprocessor systems-on-chip modelling. Des. Automat. Embedded Syst. 11 4 (2007) 285-311
22. R.L. Moigne, O. Pasquier, J.-P. Calvez, A generic RTOS model for real-time systems simulation with SystemC, in: Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04), vol. 3, IEEE Computer Society, 2004.
23. Muth J.F., and Thompson G.L. Industrial Scheduling (1963), Prentice-Hall International, Englewood Cliffs, NY, USA
24. Pimentel A.D., Erbas C., and Polstra S. A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans. Comput. 55 2 (2006) 99-112
25. Pimentel A.D., Hertzberger L.O., Lieverse P., van derWolf P., and Deprettere E.F. Exploring embedded-systems architectures with artemis. IEEE Comput. 34 11 (2001) 57-63
26. P. Pop, P. Eles, Z. Peng, Bus access optimization for distributed embedded systems based on schedulability analysis, in: Proceedings of the Conference on Design, Automation and Test in Europe (DATE'00), ACM, New York, NY, USA, 2000.
27. J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, B. Becker, A Definition and classification of timing anomalies, in: Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2006.
28. Richter K., Jersak M., and Ernst R. A formal approach to MpSoC performance verification. IEEE Comput. 36 4 (2003) 60-67
29. Schmitz M.T., Al-Hashimi B.M., and Eles P. System-Level Design Techniques for Energy-Efficient Embedded Systems (2004), Kluwer Academic Publishers, Norwell, MA, USA
30. L. Thiele, S. Chakraborty, M. Naedele, Real-time calculus for scheduling hard real-time systems, in: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 4, Geneva, Switzerland, 2000.
31. Tripakis S., and Altisen K. Implementation of timed automata: an issue of semantics or modeling?. Lecture Notes in Comput. Sci. 3829 (2005) 273-288