Improved interval-based characterization of fixed-point LTI systems with feedback loops

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 11, 2007, Pages 1923-1933

  López, Juan A ^a   Carreras, Carlos ^a   Nieto Taladriz, Octavio ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

Affine arithmetic (AA); Design automation; Digital filter word length effects; Interval arithmetic (IA); Linear systems

Indexed keywords

AFFINE ARITHMETIC (AA); CHARACTERIZATION TECHNIQUES; DESIGN AUTOMATION; FEED-BACK LOOPS; FIXED-POINT CHARACTERIZATIONS; GUARANTEED BOUNDS; INTERVAL ARITHMETIC (IA); LTI SYSTEMS; NON-LINEAR BEHAVIORS; OVER SIZINGS; QUANTIZATION OPERATIONS; QUANTIZED LINEAR SYSTEMS; RUN-TIME;

COMPUTER AIDED DESIGN; CONTROL THEORY; DIGITAL FILTERS; FEEDBACK; LINEAR SYSTEMS;

DIGITAL ARITHMETIC;

EID: 49149085661     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.896306     Document Type: Article

References (37)

1. L. B. Jackson, "Roundoff-noise analysis for fixed-point digital filters realized in cascade or parallel form," IEEE Trans. Audio Electroacoust., vol. AU-18, no. 2, pp. 107-122, Jun. 1970.
2. L. B. Jackson, Digital Filters and Signal Processing. Boston, MA: Kluwer, 1986.
3. R. A. Roberts and C. T. Mullis, Digital Signal Processing. Reading, MA: Addison-Wesley, 1987.
4. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
5. G. A. Constantinides et al., "Wordlength optimization for linear digital signal processing," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 10, pp. 1432-1442, Oct. 2003.
6. G. Li and Z. Zhao, "On the generalized DFIIt structure and its state-space realization in digital filter implementation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 4, pp. 769-778, Apr. 2004.
7. G. Caffarena et al., "Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 5, pp. 339-343, May 2006.
8. W. Sung and K.-I. Kum, "Simulation-based word-length optimization method for fixed-point digital signal processing systems," IEEE Trans. Signal Process., vol. 43, no. 12, pp. 3087-3090, Dec. 1995.
9. M. Willems et al., "FRIDGE: An interactive fixed-point code generation environment for hw/sw-codesign," in Proc. ICASSP, 1997, pp. 287-290.
10. R. Cmar et al., "A methodology and design environment for DSP ASIC fixed point refinement," in Proc. DATE, 1999, pp. 271-276.
11. C. Shi and R. W. Brodersen, "Automated fixed-point data-type optimization tool for signal processing and communication systems," in Proc. DAC, 2004, pp. 478-483.
12. T. J. Todman et al., "Reconfigurable computing: Architectures and design methods," Proc. Inst. Electr. Eng.-Computers and Digital Tech., vol. 152, no. 2, pp. 193-207, Mar. 2005.
13. G. Caffarena et al., "Design of OFDM-based adaptive equalizer for WLAN: Implementation issues," Mediterr. J. Electron. Commun., vol. 1, no. 1, pp. 25-34, 2005.
14. B.Wu, J. Zhu, and F. N. Najm, "Dynamic range estimation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 9, pp. 1618- 1636, Sep. 2006.
15. B. Hayes, "A lucid interval," Amer. Sci., vol. 91, no. 6, pp. 484-488, 2003.
16. V. Paruthi et al., "Automatic data path abstraction for verification of large scale designs," in Proc. ICCD, 1998, pp. 192-194.
17. C. Carreras, J. A. López et al., "Bit-width selection for data-path implementations," in Proc. Int. Symp. Syst. Synthesis, 1999, pp. 114-119.
18. J. A. López et al., "Fast characterization of the noise bounds derived from coefficient and signal quantization," in Proc. ISCAS, 2003, vol. 4, pp. 309-312.
19. A. Benedetti and P. Perona, "Bit-width optimization for configurable DSP's by multi-interval analysis," in Proc. Asilomar Conf. Signals, Syst. and Comput., 2000, vol. 1, pp. 355-359.
20. J. Stolfi and L. H. Figueiredo, Self-Validated Numerical Methods and Applications. Monograph for 21st Brazilian Mathematics Colloquium. Rio de Janeiro: IMPA, 1997.
21. C. F. Fang et al., "Fast, accurate static analysis for fixed-point finiteprecision effects in DSP designs," in Proc. ICCAD, 2003, pp. 275-282.
22. D. Lee et al., "Accuracy guaranteed bit-width optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 10, pp. 1990- 2000, Oct. 2006.
23. Y. Pu and Y. Ha, "An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model," in Proc. ASP-DAC, 2006, pp. 886-891.
24. J. A. López, "Evaluación de los Efectos de Cuantificación en las Estructuras de Filtros Digitales Utilizando Técnicas de Simulación Basadas en Extensiones de Intervalos," Ph.D. dissertation, Univ. Politécnica de Madrid, Madrid, Spain, 2004.
25. J. A. López et al., "Analysis of limit cycles by means of affine arithmetic computer-aided tests," in Proc. EUSIPCO, 2004, pp. 991-994.
26. H. Shou et al., "Modified affine arithmetic is more accurate than centered interval arithmetic or affine arithmetic," in Proc. 10th IMA Int. Conf. Math. Surfaces, 2003, vol. 2768, pp. 355-365.
27. R. Anguelov and S. Markov, "Wrapping effect and wrapping function," Reliab. Comput., vol. 4, no. 4, pp. 311-330, Nov. 1998.
28. C. Carreras and I. D. Walker, "Interval methods for fault-tree analysis in robotics," IEEE Trans. Rel., vol. 50, no. 1, pp. 3-11, Mar. 2001.
29. I. D. Walker, C. Carreras et al., "Extension versus bending for continuum robots," Int. J. Adv. Robot. Syst., vol. 3, no. 2, pp. 171-178, 2006.
30. N. Doi et al., "Minimization of fractional wordlength on fixed-point conversion for high-level synthesis," in Proc. ASP-DAC, 2004, pp. 80-85.
31. S. Roy and P. Banerjee, "An algorithm for trading off quantization error with hardware resources forMATLAB-based FPGA design," IEEE Trans. Comput., vol. 54, no. 7, pp. 886-896, Jul. 2005.
32. M. Stephenson et al., "Bitwidth analysis with application to silicon compilation," in Proc. ACM Conf. Programming Language Design and Implementation (SIGPLAN), 2000, pp. 108-120.
33. S. Mahlke et al., "Bitwidth cognizant architecture synthesis of custom hardware accelerators," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 11, pp. 1355-1371, Nov. 2001.
34. P. Banerjee et al., "Overview of a compiler for synthesizing MATLAB programs onto FPGAs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 3, pp. 312-324, Mar. 2004.
35. M. L. Chang and S. Hauck, "Précis: A usercentric word-length optimization tool," IEEE Des. Test Comput., vol. 22, no. 4, pp. 349-361, Jul./Aug. 2005.
36. J. Carletta et al., "Determining appropriate precisions for signals in fixedpoint IIR filters," in Proc. DAC, 2003, pp. 656-661.
37. P. Belanovic and M. Rupp, "Automated floating-point to fixed-point conversion with the fixify environment," in Proc. IEEE Int. Workshop RSP, 2005, pp. 172-178.