Wordlength optimization for linear digital signal processing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 10, 2003, Pages 1432-1442

  Constantinides, George A ^a   Cheung, Peter Y K ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Bitwidth; Digital signal processor (DSP); Optimization; Precision; Wordlength

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; LINEAR SYSTEMS; PARALLEL PROCESSING SYSTEMS;

BITWIDTH; LINEAR DIGITAL SIGNAL PROCESSING; MIXED-INTEGER LINEAR PROGRAM; WORDLENGTH;

LOGIC DESIGN;

EID: 0142054116     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818119     Document Type: Article

References (27)

1. G. A. Constantinides, P. Y. K. Cheung, and W. Luk, "The multiple wordlength paradigm," in Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Rohnert Park, CA, Apr.-May 2001.
2. S. K. Mitra, Digital Signal Processing. New York: McGraw-Hill, 1998.
3. G. A. Constantinides, "High level synthesis and word length optimization of digital signal processing systems," Ph.D. dissertation, Elect. Electron. Eng., Univ. London, London, U.K., 2001.
4. G. A. Constantinides and G. J. Woeginger, "The complexity of multiple wordlength assignment," Appl. Math. Lett., vol. 15, no. 2, pp. 137-140, 2002.
5. S. A. Wadekar and A. C. Parker, "Accuracy sensitive word-length selection for algorithm optimization," in Proc. Int. Conf. Computer Design, Austin, TX, Oct. 1998, pp. 54-61.
6. K.-I. Kum and W. Sung, "Combined word-length optimization and high-level synthesis of digital signal processing systems," IEEE Trans. Computer-Aided Design, vol. 20, pp. 921-930, Aug. 2001.
7. A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, "Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGA's," in Proc. Design Automation Test Eur., Munich, Germany, 2001, pp. 722-728.
8. M.-A. Cantin, Y. Savaria, and P. Lavoie, "An automatic word length determination method," in Proc. IEEE Int. Symp. Circuits Syst., 2001, pp. V-53-V-56.
9. M. Stephenson, J. Babb, and S. Amarasinghe, "Bitwidth analysis with application to silicon compilation," in Proc. SIGPLAN Program. Lang. Design Implementation, Vancouver, BC, Canada, June 2000, pp. 108-120.
10. R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, and I. Bolsens, "A methodology and design environment for DSP ASIC fixed point refinement," in Proc. Design Automation Test Eur., Munich, Germany, 1999, pp. 271-276.
11. M.-A. Cantin, Y. Savaria, and P. Lavoie, "A comparison of automatic word length optimization procedures," in Proc. IEEE Int. Symp. Circuits Syst., 2002, pp. II-612-II-615.
12. C. Inacio and D. Ombres, "The DSP decision: Fixed point or floating?," IEEE Spectrum, vol. 33, pp. 72-74, Sept. 1996.
13. G. A. Constantinides, P. Y. K. Cheung, and W. Luk, "Synthesis of saturation arithmetic architectures," ACM Trans. Design Automation Electron. Syst., vol. 8, no. 3, 2003.
14. ____, "Truncation noise in fixed-point SFG's," IEE Electron. Lett., vol. 35, no. 23, pp. 2012-2014, 1999.
15. G. DeMicheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
16. Altera Databook, Altera Corporation, San Jose, CA, 1998.
17. Field Programmable Gate Arrays. San Jose, CA: Xilinx, Inc., 2002.
18. Simulink, Natick, MA. [Online]. Available: http://www.mathworks.com.
19. S. D. Haynes, J. Stone, P. Y. K. Cheung, and W. Luk, "Video image processing with the sonic architecture," IEEE Computer, vol. 33, pp. 50-57, Apr. 2000.
20. B. L. Evans. Raster image processing on the TMS320C7X VLIW DSP. [Online]. Available: http://www.ece.utexas.edu/-bevans/hp-dsp-seminar/07_C6xImage2/sld001.htm.
21. L. Hafer. BonsaiG. [Online]. Available: http://www.cs.sfu.ca/-lou/BonsaiG
22. C. Lee, D. Kirovski, I. Hong, and M. Potkonjak, "DSP QUANT: Design, validation, and applications of DSP hard real-time benchmark," in Proc. IEEE Int. Conf. Acoustics Speech Signal Process., vol. 1, 1997, pp. 671-682.
23. K. Parhi, VLSI Digital Signal Process. Systems. New York: Wiley, 1999.
24. K.-I. Kum, J. Kang, and W. Sung, "Autoscaler for C: An optimizing floating-point to integer C program convertor for fixed-point digital signal processors," IEEE Trans. Circuits Syst. II, vol. 47, pp. 840-848, Sept. 2000.
25. J. Frigo, M. Gokhale, and D. Lavenier, "Evaluation of the streams-C C-to-FPGA compiler: An applications perspective," in Proc. ACM/SIGDA Int. Symp. FPGAs, 2001, pp. 134-140.
26. L. B. Jackson, "On the interaction of roundoff noise and dynamic range in digital filters," Bell Syst. Tech. J., vol. 49, pp. 159-184, 1970.
27. G. A. Constantinides, "Perturbation analysis for word-length optimization," in Proc. IEEE Symp. Field-Programmable Custom Comput. Mach., Napa, CA, Apr. 2003, pp. 81-90.