An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 886-891

  Pu, Yu ^a   Ha, Yajun ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; ALGORITHMS; BIT ERROR RATE; COMPUTER HARDWARE; ERROR ANALYSIS; ERROR CORRECTION; MATHEMATICAL MODELS; OPTIMIZATION;

AFFINE ARITHMETIC (AA) BASED METHOD; BIT-WIDTH; BIT-WIDTH ANALYSIS METHODS; INTERVAL ARITHMETIC (IA);

DIGITAL SIGNAL PROCESSING;

EID: 33748588402     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118500     Document Type: Conference Paper

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