Accuracy-guaranteed bit-width optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 1990-1999

  Lee, Dong U ^a,b   Gaffar, Altaf Abdul ^a,c   Cheung, Ray C C ^a,c   Mencer, Oskar ^a,c   Luk, Wayne ^a,c   Constantinides, George A ^a,c  

^a IEEE   (United States)

^b University of California   (United States)

^c IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Field programmable gate arrays (FPGAs); Finite word length effects; Fixed point arithmetic; Optimization methods; Simulated annealing (SA)

Indexed keywords

FINITE WORD-LENGTH EFFECTS; FIXED-POINT ARITHMETICS; NUMERICAL ACCURACY; OPTIMIZATION METHODS;

FEEDFORWARD NEURAL NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; MATHEMATICAL MODELS; NUMERICAL METHODS; OPTIMIZATION; SIMULATED ANNEALING;

COMPUTER AIDED DESIGN;

EID: 33748288306     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.873887     Document Type: Article

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