Bit-width optimization for configurable DSP's by multi-interval analysis

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2000, Pages 355-359

  Benedetti, A ^a   Perona, P ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; DATA FLOW ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS;

ACYCLIC DATA FLOW GRAPH;

VIDEO SIGNAL PROCESSING;

EID: 0034447726     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. FPGAs make a radar signal processoron on a chip a Reality
2. Real-time 2-D feature detection on a reconfigurable computer
3. Fixed-point optimization utility for C and C++ based digital signal processing programs
4. Feature detection in analog VLSI
5. On the complexity of interval-based constraint networks