A high-throughput maximum a posteriori probability detector

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 8, 2008, Pages 1846-1858

  Ratnayake, Ruwan ^a   Kavčić, Aleksandar ^b   Wei, Gu Yeon ^a  

^a HARVARD UNIVERSITY   (United States)

^b University of Hawaii at Manoa   (United States)

Author keywords

Architectures; BCJR algorithm; Forward only algorithm; Iterative processing; Maximum a posteriori probability algorithm; Turbo; VLSI

Indexed keywords

BIT ERROR RATE; CHANNEL CAPACITY; CONFORMAL MAPPING; DETECTORS; ERROR ANALYSIS; LEARNING SYSTEMS; MAPS; OPTICAL COMMUNICATION; PROBABILITY; RISK ASSESSMENT; TECHNOLOGY;

ARCHITECTURES; BCJR ALGORITHM; BIT ERROR RATE PERFORMANCE; CAPACITY LIMITS; CIRCUIT LEVEL; CMOS TECHNOLOGIES; CORE AREA; FORWARD-ONLY ALGORITHM; HIGH THROUGHPUTS; ITERATIVE PROCESSING; MAP ALGORITHMS; MAXIMUM A POSTERIORI PROBABILITY ALGORITHM; MAXIMUM A POSTERIORI PROBABILITY DETECTOR; MEAS URED RESULTS; PIPELINED ARCHITECTURES; TURBO; TURBO PROCESSING; VLSI;

THROUGHPUT;

EID: 48849116679     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.925404     Document Type: Conference Paper

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