Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2001, Pages 1232-1236

  Zhang, Tong ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; DIGITAL SIGNAL PROCESSING; ERROR CORRECTION; MATRIX ALGEBRA; VLSI CIRCUITS;

LOW DENSITY PARITY CHECK CODES; PARALLEL DECODER;

CODES (SYMBOLS);

EID: 0035573160     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Parallel decoding architectures for low density parity check codes
2. Decoder-first code design
3. Design of good LDPC codes using girth distribution
4. On finite precision implementation of low-density parity-check codes decoder