Advanced high - K/metal gate charge trapping memories for post-45 nm node

Proceedings - 2007 Non-Volatile Memory Technology Symposium, NVMTS 07

Volumn , Issue , 2007, Pages 15-19

  Golubovic D S ^a   Boutchich, M ^a   Akil, N ^a   Van Duuren, M J ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Embedded charge trapping memories; Endurance; High K dielectrics; Metal gates; Retention

Indexed keywords

C (PROGRAMMING LANGUAGE); DURABILITY; FLASH MEMORY; GATE DIELECTRICS; HAFNIUM COMPOUNDS; HIGH-K DIELECTRIC; MEMORY ARCHITECTURE; SILICON COMPOUNDS; TITANIUM NITRIDE;

CHARGE TRAPPING MEMORY; EMBEDDED CHARGE TRAPPING MEMORY; EMBEDDED FLASH; HIGH-K/METAL GATES; MEMORY ARRAY; METAL GATE; PROGRAM/ERASE; RETENTION;

CHARGE TRAPPING;

EID: 48549083422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nvmt.2007.4389937     Document Type: Conference Paper

References (9)

1. 2 cell size using TANOS (Si - Oxide - Al2O3 - TaN) cell technology," IEDM '06 Tech. Digest, pp. 29-32, 2006.
2. M. F. Beug et al., " Sub - lithographical shirnk of twin-flash™ memory cells to the 32 nm technology node," Proc. ICMTD '07, pp.191-193, 2007.
3. R. van Schaijk et al., "Low voltage and low power embedded 2T SONOS flash memories using p-type devices and high - K materials," Solid State Electron., vol. 49, pp. 1849-1856, 2005.
4. 4/HfSiON stack for improved retention," Proc. NVSMW 2006, pp. 50-51, 2006.
5. S. H. Gu, C. W. Hsu, T. Wang, W. P. Lu, Y. H. Ku, and C. Y. Lu, "Numerical simulation of bottom oxide thickness effect on charge retention is SONOS flash memory cells," IEEE Trans. Electon Devices, vol. 54, no. 1, pp. 90-97, 2007.
6. S. Jeon, J. H. Han, J. H. Lee, S. Choi, H. Hwang, C. Kim, "High work-function metal gate and high - k dielectrics for charge trap flah memory device applications," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2654-2659, 2005.
7. G. Ribes et al., "Review on high - k dielectrics reliability issues," IEEE Trans. Devic Mater. Rel., vol 5, no. 1. pp. 5-19, 2005.
8. Y. Wang and M. H. White, "An analytical retention model for SONOS nonvolatile memory devices in the excess electron state," Solid State Electron., vol. 49, pp. 97-107, 2005.
9. Y. Yang and M. H. White, " Charge retention in scaled SONOS nonvolatile memory devices at elevated temperatures," Solid State Electron., vol. 44, pp. 949-958, 2000.