Improved first-order parameterized statistical timing analysis for handling slew and capacitance variation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 278-282

  Goyal, Ratnakar ^a   Shrivastava, Sachin ^a   Parameswaran, Harindranath ^a   Khurana, Parveen ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; PROBABILITY; PROBABILITY DISTRIBUTIONS; SENSITIVITY ANALYSIS; SYSTEMS ANALYSIS; TIME MEASUREMENT; TIMING DEVICES;

ANALYTICAL EXPRESSIONS; CAPACITANCE VARIATIONS; CASE ANALYSIS; FIRST ORDERS; INHERENT EFFECTS; OUTPUT LOADS; PARAMETERIZED; PATH ARRIVALS; POINTS OF INTERESTS; POPULAR TECHNIQUES; PROCESS PARAMETER VARIATIONS; PROCESS PARAMETERS; PROCESS VARIATIONS; SHRINKING PROCESSES; STATIC TIMING ANALYSES; STATISTICAL TIMING ANALYSES; TIMING ANALYSIS; VARIATIONS OF;

TIMING CIRCUITS;

EID: 48349102062     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.92     Document Type: Conference Paper

References (16)

1. Chandu Visweswariah, "Death, Taxes and Failing Chips", Proc. Design Automation Conference, pp. 343-347, 2003.
2. L. Zhang, Y. Hu and C.C.P. Chen, "Block-Based Statistical Timing Analysis with Extended Canonical Timing Model", Proc. Asia and South Pacific Design Automation Conference, pp. 250-253, 2005.
3. C. Visweswariah, K. Ravindran, K. Kalafala, S.G. Walker and S. Narayan, "First-Order Incremental Block-Based Timing Analysis", Proc. Design Automation Conference, pp. 331-336, 2004.
4. Hongliang Chang and Sachin S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations Using a Singal Perl-Like Traversal", Proc. ICCAD, pp. 621-625, 2003.
5. Lou Scheffer, "Explicit Computation of Performance as a Function of Process Variation", Proc. TAU, 2002.
6. Kurt Keutzer and Michael Orshansky, "From Blind Certainty to Informed Uncertainty", Proc. Intl. workshop on Timing issues in the specification and synthesis of digital systems, pp. 37-41, 2002.
7. R. Hitchcock, "Timing Verification and the Timing Analysis Program", Proc. Design Automation Conference, pp. 594-604, 1982.
8. Sachin Sapatnekar, "Timing", Kluwer Academic Publishers, 2004.
9. R. B. Hitchcock, G.L. Smith and D.D. Cheng, "Timing Analysis of Computer Hardware", IBM Journal of Research and Development, 26, pp. 100-105, January 1982.
10. DR Tryon, F.M. Armstrong and M.R. Reiter, "Statistical failure analysis of system timing", IBM Journal of Research and Development, July 1984.
11. J.J.Liou, K.T. Cheng, S. Kundu, and A. Krstic, "Fast Statistical Timing Analysis by Probabilistic Event Propagation", Proc. 2001 Design Automation Conference, pp. 661-666.
12. Y.Liu, S.R. Nassif, L.T. Pileggi, and A.J. Strojwas, "Impact of Interconnect Variations on the Clock Skew of Gigahertz Microprocessors" , Proc. Design Automation Conference, pp. 168-171, 2000.
13. A Devgan and C Kashyap, "Block-based Static Timing Analysis with Uncertainty", ICCAD-2003.
14. Chandu et al, "First-Order Parameterized Block-Based Statistical Timing Analysis", TAU-04.
15. A Papoulis, "Probability, Random Variables, and Stochastic Process", McGraw Hill, 1984.
16. D.F. Morrison, "Multivariate Statistical Methods", New York: McGraw Hill, 1976.