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Volumn , Issue , 2007, Pages 196-201

Domain-specific hybrid FPGA: Architecture and floating point applications

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 48149112303     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380647     Document Type: Conference Paper
Times cited : (23)

References (11)
  • 1
    • 33745805907 scopus 로고    scopus 로고
    • Measuring the gap between FPGAs and ASICs
    • New York, NY, USA: ACM Press
    • I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," in Proc. FPGA. New York, NY, USA: ACM Press, 2006, pp. 21-30.
    • (2006) Proc. FPGA , pp. 21-30
    • Kuon, I.1    Rose, J.2
  • 2
    • 84963954581 scopus 로고    scopus 로고
    • Totem: Custom Reconfigurable Array Generation
    • K. Compton and S. Hauck, "Totem: Custom Reconfigurable Array Generation," in Proc. FCCM, 2001, pp. 111-119.
    • (2001) Proc. FCCM , pp. 111-119
    • Compton, K.1    Hauck, S.2
  • 3
    • 33746461451 scopus 로고    scopus 로고
    • Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits
    • A. Ye and J. Rose, "Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits," IEEE Trans. VLSI, vol. 14, no. 5, pp. 462-473, 2006.
    • (2006) IEEE Trans. VLSI , vol.14 , Issue.5 , pp. 462-473
    • Ye, A.1    Rose, J.2
  • 4
    • 79955148940 scopus 로고    scopus 로고
    • Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
    • E. Roesler and B. Nelson, "Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture," in Proc. FPL, 2002, pp. 637-646.
    • (2002) Proc. FPL , pp. 637-646
    • Roesler, E.1    Nelson, B.2
  • 6
    • 34547473719 scopus 로고    scopus 로고
    • Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
    • C. Ho, P. Leong, W. Luk, S. Wilton, and S. Lopez-Buedo, "Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs," in Proc. FCCM, 2006, pp. 35-44.
    • (2006) Proc. FCCM , pp. 35-44
    • Ho, C.1    Leong, P.2    Luk, W.3    Wilton, S.4    Lopez-Buedo, S.5
  • 7
    • 2142660781 scopus 로고    scopus 로고
    • The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
    • March
    • E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," IEEE Trans. VLSI, vol. 12, no. 3, pp. 288-298, March 2004.
    • (2004) IEEE Trans. VLSI , vol.12 , Issue.3 , pp. 288-298
    • Ahmed, E.1    Rose, J.2
  • 8
    • 35248884474 scopus 로고    scopus 로고
    • ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
    • B. Mei, S. Vernalde, D. Verkest, H. Man, and R. Lauwereins, "ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," in Proc. FPL, 2003, pp. 61-70.
    • (2003) Proc. FPL , pp. 61-70
    • Mei, B.1    Vernalde, S.2    Verkest, D.3    Man, H.4    Lauwereins, R.5
  • 9
    • 34748872044 scopus 로고    scopus 로고
    • A Synthesizable Datapath-Oriented Embedded FPGA Fabric
    • S. Wilton, C. Ho, P. Leong, W. Luk, and B. Quinton, "A Synthesizable Datapath-Oriented Embedded FPGA Fabric," in Proc. FPGA, 2007, pp. 33-41.
    • (2007) Proc. FPGA , pp. 33-41
    • Wilton, S.1    Ho, C.2    Leong, P.3    Luk, W.4    Quinton, B.5
  • 10
    • 48149086088 scopus 로고    scopus 로고
    • Xilinx Inc, Product Specification
    • Xilinx Inc., Floating-Point Operator v1.0. Product Specification, 2005.
    • (2005) Floating-Point Operator v1.0


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.