Novel optimizations for hardware floating-point units in a modern FPGA architecture

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438, Issue , 2002, Pages 637-646

  Roesler, Eric ^a   Nelson, Brent ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION CIRCUITS; AREA SAVINGS; CIRCUIT FUNCTIONS; DESIGN TRADEOFF; FLOATING POINT UNITS; FLOATING-POINT COMPUTATION; FPGA ARCHITECTURES; HEAT TRANSFER PROBLEMS; HIGH DENSITY; MULTIPLIER BLOCKS;

DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY MULTIPLYING CIRCUITS; MULTIPLYING CIRCUITS; SHIFT REGISTERS;

COMPUTER ARCHITECTURE;

EID: 79955148940     PISSN: 03029743     EISSN: 16113349     Source Type: Journal    
DOI: 10.1007/3-540-46117-5_66     Document Type: Article

References (10)

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