An FPGA implementation for a high throughput adaptive filter using distributed arithmetic

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 324-325

  Allred, Daniel J ^a   Huang, Walter ^a   Krishnan, Venkatesh ^a   Yoo, Heejong ^a   Anderson, David V ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY NUMBERS; BIT SERIAL COMPUTATIONS; DISTRIBUTED ARITHMETIC;

ADAPTIVE FILTERING; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; FIR FILTERS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; PROBLEM SOLVING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 18644375706     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2004.15     Document Type: Conference Paper

References (3)

1. C. F. N. Cowan and J. Mavor. New digital-adaptive filter implementation using distributed-arithmetic techniques. IEE Proceedings, 128, Pt. F(4):225-230, August 1981.
2. C. H. Wei and J. J. Lou. Multimemory block structure for implementing a digital adaptive filter using distributed arithmetic. IEE Proceedings, 133, Pt. G(1):19-26, February 1986.
3. S. A. White. Applications of distributed arithmetic to digital signal processing: A tutorial review. IEEE ASSP Magazine, 6:4-19, July 1989.