Embedded Twin MONOS Flash Memories with 4ns and 15ns Fast Access Times

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 207-208

  Ogura, Tomoko ^a   Ogura, Nori ^a   Kirihara, Masaharu ^a   Park, Ki Tae ^a   Baba, Yoshitaka ^a   Sekine, Masao ^a   Shimeno, Koji ^a  

^a Halo LSI Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; OXIDES; SYSTEMS ANALYSIS;

ACCESS TIMES;

FLASH MEMORY;

EID: 0141538191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Y. Hayashi, et. al, "Twin MONOS cell with dual control gates", VLSI Technology Symposium, 2000.
2. T. Saito, et. al, "Single Bit erasable Twin MONOS for High density EEPROM application", Non-volatile Workshop, 2003.
3. L. Heller, et. al, "High Sensitivity Charge-Transfer Sense Amplifer", IEEE JSSC, Vo. SC-11, No.4 1976, pp.596-601.