Memory hierarchy performance measurement of commercial dual-core desktop processors

Journal of Systems Architecture

Volumn 54, Issue 8, 2008, Pages 816-828

  Peng, Lu ^a   Peir, Jih Kwon ^b   Prakash, Tribuvan K ^a   Staelin, Carl ^c   Chen, Yen Kuang ^d   Koppelman, David ^a  

^a LOUISIANA STATE UNIVERSITY   (United States)

^b University of Florida   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Core 2 Duo; Memory; Multi core processor; Performance evaluation

Indexed keywords

COMPUTER HARDWARE; MICROPROCESSOR CHIPS; SCALABILITY; SPECIFICATIONS;

(OTDR) TECHNOLOGY; ATHLON 64; CHIP MULTI PROCESSOR (CMP); DESIGN SPECIFICATIONS; DUAL CORES; ELSEVIER (CO); L2 CACHE; MAINSTREAM (MS); MEMORY HIERARCHIES; MEMORY HIERARCHY PERFORMANCE; MICRO ARCHITECTURES; MULTI-THREADED; ON CHIP COMMUNICATIONS; OVERALL EXECUTION; PENTIUM; PENTIUM 4; PERFORMANCE MEASUREMENT (QUALITY); PERFORMANCE SCALABILITY; PROCESSOR ARCHITECTURES; RESOURCE SHARING; THROUGHPUT MEASUREMENTS;

INDUSTRIAL MANAGEMENT;

EID: 48149094931     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2008.02.004     Document Type: Article

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