Memory performance and scalability of intel's and AMD's dual-core processors: A case study

Conference Proceedings of the IEEE International Performance, Computing, and Communications Conference

Volumn , Issue , 2007, Pages 55-64

  Peng, Lu ^a   Peir, Jih Kwon ^b   Prakash, Tribuvan K ^a   Chen, Yen Kuang ^c   Koppelman, David ^a  

^a LOUISIANA STATE UNIVERSITY   (United States)

^b J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE-TO-CACHE COMMUNICATION; CHIP MULTIPROCESSOR (CMP); DUAL-CORE PROCESSORS; INTEL PENTIUM D;

BUFFER STORAGE; MICROPROCESSOR CHIPS; SCALABILITY; SPECIFICATIONS;

DATA STORAGE EQUIPMENT;

EID: 36348949051     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PCCC.2007.358879     Document Type: Conference Paper

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