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1
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33847711795
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High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS
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A. Pouydebasque, B. Dumont, S. Denorme, F. Wacquant, M. Bidaud, C. Laviron, A. Halimaoui, C. Chaton, J.D. Chapon, P. Gouraud, F. Leverd, H. Bernard, S. Warrick, D. Delille, K. Romanjek, R. Gwoziecki, N. Planes, S. Vadot, I. Pouillouxl, F. Arnaud, F. Boeuf, T. Skotnicki, "High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS", IEDM Technical digests p. 663, 2005.
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(2005)
IEDM Technical digests
, pp. 663
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Pouydebasque, A.1
Dumont, B.2
Denorme, S.3
Wacquant, F.4
Bidaud, M.5
Laviron, C.6
Halimaoui, A.7
Chaton, C.8
Chapon, J.D.9
Gouraud, P.10
Leverd, F.11
Bernard, H.12
Warrick, S.13
Delille, D.14
Romanjek, K.15
Gwoziecki, R.16
Planes, N.17
Vadot, S.18
Pouillouxl, I.19
Arnaud, F.20
Boeuf, F.21
Skotnicki, T.22
more..
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2
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33847715120
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M. Okuno, K. Okabe, T. Sakuma, K. Suzuki, T. Miyashita, T. Yao, H. Morioka, M. Terahara, Y. Kojima, H. Watatani, K. Sugimoto, T. Watanabe, Y. Hayami, T. Mori, T. Kubo, Y. Iba, I. Sugiura, H. Fukutome, Y. Morisaki, H. Minakata, K. Ikeda, S. Kishii, N.Shimizu, T. Tanaka, S. Asai, M. Nakaishi, S. Fukuyama, A. Tsukune, M. Yamabe, I. Hanyuu, M. Miyajima, M. Kase, K.Watanabe, S. Satoh, and T. Sugii., 45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications, IEDM Technical digests, p.52, 2005.
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M. Okuno, K. Okabe, T. Sakuma, K. Suzuki, T. Miyashita, T. Yao, H. Morioka, M. Terahara, Y. Kojima, H. Watatani, K. Sugimoto, T. Watanabe, Y. Hayami, T. Mori, T. Kubo, Y. Iba, I. Sugiura, H. Fukutome, Y. Morisaki, H. Minakata, K. Ikeda, S. Kishii, N.Shimizu, T. Tanaka, S. Asai, M. Nakaishi, S. Fukuyama, A. Tsukune, M. Yamabe, I. Hanyuu, M. Miyajima, M. Kase, K.Watanabe, S. Satoh, and T. Sugii., "45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications", IEDM Technical digests, p.52, 2005.
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3
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33846276277
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A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokum, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, I. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima and F. Matsuoka, High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique, IEDM Technical digests, p229, 2005.
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A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokum, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, I. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima and F. Matsuoka, "High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique", IEDM Technical digests, p229, 2005.
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4
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33646045529
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K. Adachi, K. Ohuchi, N. Aoki, H. Tsujii, T. Ito, H. Itokawa, K. Matsuo, K. Suguro, Y. Honguh, N. Tamaoki, K. Ishimaru, and H. Ishiuchi, Issues and optimization of millisecond anneal process for 45 nm node and beyond, Symposium on VLSI Technology Digest of Technical Papers, p.142, 2005.
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K. Adachi, K. Ohuchi, N. Aoki, H. Tsujii, T. Ito, H. Itokawa, K. Matsuo, K. Suguro, Y. Honguh, N. Tamaoki, K. Ishimaru, and H. Ishiuchi, "Issues and optimization of millisecond anneal process for 45 nm node and beyond", Symposium on VLSI Technology Digest of Technical Papers, p.142, 2005.
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5
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33745170708
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A. Shima, Y. Wang, D. Upadhyaya, L. Feng, S. Talwar, and A. Hiraiwa, Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing, Symposium on VLSI Technology Digest of Technical Papers, p.144, 2005.
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A. Shima, Y. Wang, D. Upadhyaya, L. Feng, S. Talwar, and A. Hiraiwa, "Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing", Symposium on VLSI Technology Digest of Technical Papers, p.144, 2005.
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6
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41149175553
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T. Yamamoto, T. Kubo, T. Sukegawa, K. Hashimoto, and M. Kase, Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-implantation for Sub-30-nm Strained CMOS Devices, Symposium on VLSI Technology Digest of Technical Papers, p.234, 2006.
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T. Yamamoto, T. Kubo, T. Sukegawa, K. Hashimoto, and M. Kase, "Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-implantation for Sub-30-nm Strained CMOS Devices", Symposium on VLSI Technology Digest of Technical Papers, p.234, 2006.
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7
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21644471710
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Simulation of high-temperature millisecond annealing-based on atomistic modeling of boron diffusion/activation in silicon
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M. Hane, T. Ikezawa, T. Matsuda and S. Shishiguchi, "Simulation of high-temperature millisecond annealing-based on atomistic modeling of boron diffusion/activation in silicon", IEDM Technical digests, p. 975, 2004.
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(2004)
IEDM Technical digests
, pp. 975
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Hane, M.1
Ikezawa, T.2
Matsuda, T.3
Shishiguchi, S.4
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8
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41149085629
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M. Togo, T. Suzuki, E. Hasegawa, S. Koyama, T. Fukai, A. Sakakidani, S. Miyake, T. Watanabe, I. Yamamoto, M. Tanaka, Y. Kawashima, Y. Kunimune, M. Ikeda, and K. !mai, Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm Node and Beyond, and Its Countermeasure Using Nitrogen Implanted Poly-Si, Symposium on VLSI Technology Digest of Technical Papers, p.36, 2006.
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M. Togo, T. Suzuki, E. Hasegawa, S. Koyama, T. Fukai, A. Sakakidani, S. Miyake, T. Watanabe, I. Yamamoto, M. Tanaka, Y. Kawashima, Y. Kunimune, M. Ikeda, and K. !mai, "Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm Node and Beyond, and Its Countermeasure Using Nitrogen Implanted Poly-Si", Symposium on VLSI Technology Digest of Technical Papers, p.36, 2006.
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