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Volumn 1522, Issue , 1998, Pages 133-148

Automatic verification of mixed-level logic circuits

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; LOGIC CIRCUITS; PIECEWISE LINEAR TECHNIQUES; SPECIFICATIONS; TIMING CIRCUITS;

EID: 84948971120     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49519-3_10     Document Type: Conference Paper
Times cited : (4)

References (4)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.