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Volumn 1522, Issue , 1998, Pages 133-148
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Automatic verification of mixed-level logic circuits
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER AIDED DESIGN;
FORMAL METHODS;
LOGIC CIRCUITS;
PIECEWISE LINEAR TECHNIQUES;
SPECIFICATIONS;
TIMING CIRCUITS;
ANALOG COMPONENTS;
AUTOMATIC VERIFICATION;
DECISION PROCEDURE;
DIGITAL SYSTEM;
LEVEL OF ABSTRACTION;
MIXED LEVELS;
PIECEWISE LINEAR;
SPECIFICATION AND VERIFICATION;
COMPUTER CIRCUITS;
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EID: 84948971120
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/3-540-49519-3_10 Document Type: Conference Paper |
Times cited : (4)
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References (4)
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