Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 18-19

  Yu, H Y ^a   Chang, S Z ^b   Veloso, A ^a   Lauwers, A ^a   Adelmann, C ^a   Onsia, B ^a   Van Elshocht, S ^a   Singanamalla, R ^a   Demand, M ^a   Vos, R ^a   Kauerauf, T ^a   Brus, S ^a   Shi, X ^a   Kubicek, S ^a   Vrancken, C ^a   Mitsuhashi, R ^c   Lehnen, P ^a   Kittl, J ^d   Niwa, M ^c   Yin, K M ^e   Hoffmann, T ^a   Degendt, S ^a   Jurczak, M ^a   Absil, P ^a   Biesemans, S ^a   more..

^a IMEC   (Belgium)

^b NXP TSMC Research Center   (Belgium)

^c Matsushita   (Belgium)

^d TI   (Belgium)

^e IMEC ^*

Author keywords

[No Author keywords available]

Indexed keywords

VLSI TECHNOLOGIES;

EID: 47249087741     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339710     Document Type: Conference Paper

References (5)

1. T. Hoffmann. IEDM. p.10-3(2006);
2. H.Y. Yu, Tech. VLSI, p,120(2006);
3. T. Uo, EDL, p.640, (2006);
4. H.S. Jung, Tech. VLSI, p.204 (2006);
5. Y.H. Kim, IEDM. p.657 (2005)