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Volumn , Issue , 2007, Pages 176-179

Technology and application of 3D interconnect

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CELLULAR RADIO SYSTEMS; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; TECHNOLOGY;

EID: 47349110849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2007.4299567     Document Type: Conference Paper
Times cited : (7)

References (12)
  • 1
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep-submicron interconnect performance and system-on-chip integration
    • May
    • K. Banerjee, et al., "3-D ICs: A novel chip design for improving deep-submicron interconnect performance and system-on-chip integration," in Proc. IEEE, vol. 89, pp. 602-633, May 2001.
    • (2001) Proc. IEEE , vol.89 , pp. 602-633
    • Banerjee, K.1
  • 2
    • 47349095389 scopus 로고    scopus 로고
    • K. W. Guarini, et al., Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated Circuit(IC) fabrication, in Proc. IEDM, 2002 pp. 16.6.1-16.6.3.
    • K. W. Guarini, et al., "Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated Circuit(IC) fabrication", in Proc. IEDM, 2002 pp. 16.6.1-16.6.3.
  • 3
    • 34250852813 scopus 로고    scopus 로고
    • Exploration of the scaling limits of 3D integration
    • 0970-Y02-01
    • S. Pozder, et al., "Exploration of the scaling limits of 3D integration", in Mater. Res. Soc. Symp. Proc., vol. 970, 2006, 0970-Y02-01.
    • (2006) Mater. Res. Soc. Symp. Proc , vol.970
    • Pozder, S.1
  • 4
    • 0034822219 scopus 로고    scopus 로고
    • Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation
    • Y. Tomita, et al., "Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation," in Proc. Electronic Components and Techn. Conf., 2001, pp. 353-360.
    • (2001) Proc. Electronic Components and Techn. Conf , pp. 353-360
    • Tomita, Y.1
  • 6
    • 84948471389 scopus 로고    scopus 로고
    • Fabrication techniques for three-dimensional integrated circuits
    • San Jose, CA
    • R. Reif, et al., "Fabrication techniques for three-dimensional integrated circuits," in Proc. ISQED, San Jose, CA, 2002, pp. 33-37.
    • (2002) Proc. ISQED , pp. 33-37
    • Reif, R.1
  • 7
    • 0036458722 scopus 로고    scopus 로고
    • Low temperature oxide-bonded three-dimensional integrated circuits
    • K. Warner, "Low temperature oxide-bonded three-dimensional integrated circuits," in Proc. IEEE Intern. SOI Conf., 2002, pp. 123-125.
    • (2002) Proc. IEEE Intern. SOI Conf , pp. 123-125
    • Warner, K.1
  • 8
    • 0036963601 scopus 로고    scopus 로고
    • Wafer bonding using dielectric polymer thin films in 3D integration
    • Y. Kwon, et al., "Wafer bonding using dielectric polymer thin films in 3D integration," in Mat. Res. Soc. Symp. Proc., vol. 710, 2002, pp. 231-236.
    • (2002) Mat. Res. Soc. Symp. Proc , vol.710 , pp. 231-236
    • Kwon, Y.1
  • 9
    • 34748923685 scopus 로고    scopus 로고
    • Three dimensional chip stacking using a wafer-to-wafer integration
    • to be published
    • R. Chatterjee, et al., "Three dimensional chip stacking using a wafer-to-wafer integration", in Proc. IITC, 2007 (to be published).
    • (2007) Proc. IITC
    • Chatterjee, R.1
  • 10
    • 2442686519 scopus 로고    scopus 로고
    • A 160 Gb/s interface design configuration for multichip LSI
    • T. Ezaki, et al., "A 160 Gb/s interface design configuration for multichip LSI," in Proc. Intern. Solid-State Circuits Conf., 2004, pp. 140-141.
    • (2004) Proc. Intern. Solid-State Circuits Conf , pp. 140-141
    • Ezaki, T.1
  • 11
    • 47349115116 scopus 로고    scopus 로고
    • Inter-strata characteristics and signal transmission in three-dimensional (3D) integration technology
    • to be published
    • S. M. Alam, et al., "Inter-strata characteristics and signal transmission in three-dimensional (3D) integration technology," in Proc. ISQED, 2007, (to be published).
    • (2007) Proc. ISQED
    • Alam, S.M.1
  • 12
    • 34748889075 scopus 로고    scopus 로고
    • Challenges for 3D IC integration bonding quality and thermal management
    • to be published
    • P. Leduc, et al., "Challenges for 3D IC integration bonding quality and thermal management," in Proc. IITC, 2007 (to be published).
    • (2007) Proc. IITC
    • Leduc, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.