메뉴 건너뛰기




Volumn , Issue , 2007, Pages 73-81

A reconfigurable hardware interface for a modern computing system

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; GENERAL PURPOSE COMPUTERS; RECONFIGURABLE ARCHITECTURES;

EID: 47349105997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.49     Document Type: Conference Paper
Times cited : (19)

References (28)
  • 3
    • 33749549867 scopus 로고    scopus 로고
    • S5: The architecture and development flow of a software configurable processor
    • Dec
    • Jeffrey M. Arnold. S5: The architecture and development flow of a software configurable processor. In IEEE International Conference on Field Programmable Technology, pages 121-128, Dec 2005.
    • (2005) IEEE International Conference on Field Programmable Technology , pp. 121-128
    • Arnold, J.M.1
  • 6
    • 33746112657 scopus 로고    scopus 로고
    • An execution environment for reconfigurable computing
    • Washington, DC, USA, IEEE Computer Society
    • Wenyin Fu and Katherine Compton. An execution environment for reconfigurable computing. In IEEE Symposium on Field-Programmable Custom Computing Machines, pages 149-158, Washington, DC, USA, 2005. IEEE Computer Society.
    • (2005) IEEE Symposium on Field-Programmable Custom Computing Machines , pp. 149-158
    • Fu, W.1    Compton, K.2
  • 10
    • 0031360911 scopus 로고    scopus 로고
    • Garp: A MIPS processor with a reconfigurable coprocessor
    • Washington, DC, USA, IEEE Computer Society
    • J. R. Hauser and J. Wawrzynek. Garp: a MIPS processor with a reconfigurable coprocessor. In IEEE Symposium on FPGA-Based Custom Computing Machines, page 12, Washington, DC, USA, 1997. IEEE Computer Society.
    • (1997) IEEE Symposium on FPGA-Based Custom Computing Machines , pp. 12
    • Hauser, J.R.1    Wawrzynek, J.2
  • 16
    • 84947248063 scopus 로고    scopus 로고
    • V. Nollet, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins. Designing an operating system for a heterogeneous reconfigurable SoC. In International Symposium on Parallel and Distributed Processing, page 174.1, Washington, DC, USA, 2003. IEEE Computer Society.
    • V. Nollet, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins. Designing an operating system for a heterogeneous reconfigurable SoC. In International Symposium on Parallel and Distributed Processing, page 174.1, Washington, DC, USA, 2003. IEEE Computer Society.
  • 18
    • 33746304808 scopus 로고    scopus 로고
    • JoAnn M. Paul. Scenario-oriented design for single chip heterogeneous multiprocessor. In IEEE International Parallel and Distributed Processing Symposium, page 227.2, Washington, DC, USA, 2005. IEEE Computer Society.
    • JoAnn M. Paul. Scenario-oriented design for single chip heterogeneous multiprocessor. In IEEE International Parallel and Distributed Processing Symposium, page 227.2, Washington, DC, USA, 2005. IEEE Computer Society.
  • 21
    • 47349112870 scopus 로고    scopus 로고
    • Sun Microsystems. Ultrasparc user's manual. 1997.
    • Sun Microsystems. Ultrasparc user's manual. 1997.
  • 22
    • 11244281436 scopus 로고    scopus 로고
    • Programming transparency and portable hardware interfacing: Towards general-purpose reconfigurable computing
    • Washington, DC, USA, IEEE Computer Society
    • Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Programming transparency and portable hardware interfacing: Towards general-purpose reconfigurable computing. In IEEE Conference on Application-Specific Systems, Architectures and Processors, pages 339-351, Washington, DC, USA, 2004. IEEE Computer Society.
    • (2004) IEEE Conference on Application-Specific Systems, Architectures and Processors , pp. 339-351
    • Vuletić, M.1    Pozzi, L.2    Ienne, P.3
  • 23
    • 17844387820 scopus 로고    scopus 로고
    • Miljan Vuletic, Laura Pozzi, and Paolo Ienne. Seamless hardware-software integration in reconfigurable computing systems. IEEE Des. Test, 22(2):102-113, 2005.
    • Miljan Vuletic, Laura Pozzi, and Paolo Ienne. Seamless hardware-software integration in reconfigurable computing systems. IEEE Des. Test, 22(2):102-113, 2005.
  • 25
    • 0030399910 scopus 로고    scopus 로고
    • OneChip: An FPGA processor with reconfigurable logic
    • Kenneth L. Pocek and Jeffrey Arnold, editors, Los Alamitos, CA, IEEE Computer Society Press
    • R.D. Wittig and P. Chow. OneChip: An FPGA processor with reconfigurable logic. In Kenneth L. Pocek and Jeffrey Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 126-135, Los Alamitos, CA, 1996. IEEE Computer Society Press.
    • (1996) IEEE Symposium on FPGAs for Custom Computing Machines , pp. 126-135
    • Wittig, R.D.1    Chow, P.2
  • 26
    • 33846596030 scopus 로고    scopus 로고
    • Xilinx Inc. Virtex-II Pro and Virtex-II Pro X platform FPGAs
    • Xilinx Inc. Virtex-II Pro and Virtex-II Pro X platform FPGAs: Complete data sheet. 2005.
    • (2005) Complete data sheet
  • 27
    • 47349100666 scopus 로고    scopus 로고
    • Xilinx Inc. Virtex-4 family overview
    • Xilinx Inc. Virtex-4 family overview. 2006.
    • (2006)
  • 28
    • 0033703884 scopus 로고    scopus 로고
    • Chimaera: A high-performance architecture with a tightly-coupled reconfigurable functional unit
    • New York, NY, USA, ACM Press
    • Zhi Alex Ye, Andreas Moshovos, Scott Hauck, and Prithviraj Banerjee. Chimaera: a high-performance architecture with a tightly-coupled reconfigurable functional unit. In ACM International symposium on Computer architecture, pages 225-235, New York, NY, USA, 2000. ACM Press.
    • (2000) ACM International symposium on Computer architecture , pp. 225-235
    • Alex, Z.1    Ye, A.M.2    Hauck, S.3    Banerjee, P.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.