Seamless hardware-software integration in reconfigurable computing systems

IEEE Design and Test of Computers

Volumn 22, Issue 2, 2005, Pages 102-113

  Vuletić, Miljan ^a   Pozzi, Laura ^a   Ienne, Paolo ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS; INTERCONNECTION NETWORKS; PARALLEL PROCESSING SYSTEMS; PROGRAM TRANSLATORS; VIRTUAL STORAGE;

HARDWARE ACCELERATORS; MULTITHREADED PROGRAMMING; RECONFIGURABLE COMPUTING SYSTEMS;

COMPUTER SYSTEMS PROGRAMMING;

EID: 17844387820     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.44     Document Type: Article

References (12)

1. S. Vassiliadis et al., "The MOLEN Polymorphic Processor," IEEE Trans Computers, vol 53, no 11, Nov. 2004, pp. 1363-1375.
2. G. Brebner, P. James-Roxby, and C. Kulkarni, "Hyper-Programmable Architecture for Adaptable Networked Systems," Proc. 15th Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP 04), IEEE Press, 2004, pp. 328-338.
3. D. Andrews et al., "Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link," IEEE Micro, vol. 24, no. 4, July-Aug. 2004, pp. 42-53.
4. B. Nichols, Pthreads Programming: A POSIX Standard for Better Multiprocessing, O'Reilly and Associates, 1996.
5. A.S. Tanenbaum, Modern Operating Systems, 2nd ed., Prentice-Hall, 2001.
6. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002.
7. M. Vuletić, L. Pozzi, and P. Ienne, "Virtual Memory Window for Application-Specific Reconfigurable Coprocessors," Proc. 41st Ann. Conf. Design Automation (DAC 04), ACM Press, 2004, pp. 948-953.
8. D.E. Culler, J.P. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1999.
9. M. Vuletić, L. Pozzi, and P. Ienne, "Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing," Proc. 15th Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP 04), IEEE Press, 2004, pp. 339-351.
10. M. Vuletić, L. Pozzi, and P. Ienne, "Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors," Proc. 14th Int'l Conf. Field-Programmable Logic and Applications, LNCS 3203, Springer-Verlag, 2004, pp. 596-605.
11. L. Semeria, K. Sato, and G. De Micheli, "Synthesis of Hardware Models in C with Pointers and Complex Data Structures," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 9, no. 6, Dec. 2001, pp. 743-756.
12. C. Dubach, Java Byte Code Synthesis for Reconfigurable Computing Platforms, master's thesis, Ecole Polytechnique Fédérale de Lausanne Switzerland, 2005.