An overview of reconfigurable hardware in embedded systems

Eurasip Journal on Embedded Systems

Volumn 2006, Issue , 2006, Pages 1-19

  Garcia, Philip ^a   Schulte, Michael ^a   Compton, Katherine ^a   Blem, Emily ^a   Fu, Wenyin ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33749561679     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/ES/2006/56320     Document Type: Article

References (204)

1. J. Greene E. Hamdy S. Beal Antifuse field programmable gate arrays. Proceedings of the IEEE 81 7 1993 1042 1056
2. Actel Corporation Programming Antifuse Devices Application Note. Actel, Mountain View, Calif, USA, 2005, http://www.actel.com
3. G. Lu H.Singh M. Lee N. Bagherzadeh F.. Kurdahi E. M. C. Filho The mrphoSys parallel reconfigurable system. Proceedings of 5th International Euro-Par Conference on Parallel Processing (Euro-Par '99) Toulouse, France 1999 727 734
4. G. Kuzmanov G.Kuzmanov@EWI.TUDelft.NL G. Gaydadjiev G.N.Gaydadjiev@EWI. TUDelft.NL S. Vassiliadis S.Vassiliadis@EWI.TUDelft.NL The MOLEN processor prototype. Proceedings of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04) Napa Valley, Calif, USA 2004 296 299
5. D. Pramanik H. Kamberian C. Progler M. Sanie D. Pinto Cost effective strategies for ASIC masks. Proceedings of SPIE Cost and Performance in Integrated Circuit Creation Santa Clara, Calif, USA 5043 2003 142 152
6. Actel Corporation Flash FPGAs in the value-based market white paper. Actel Mountain View, Calif, USA 55900021-0 2005 http://www.actel.com
7. B. Moyer Low-power design for embedded processors. Proceedings of the IEEE 89 2001 11 1576 1587
8. A. Abnous K. Seno Y. Ichikawa M. Wan J. Rabaey Evaluation of a low-power reconfigurable DSP architecture. Proceedings of the 5th Reconfigurable Architectures Workshop (RAW '98) Orlando, Fla, USA 1998 55 60
9. O. Mencer M. Morf M. J. Flynn Hardware software tri-design of encryption for mobile communication units. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '98) Seattler, Wash, USA 5 1998 3045 3048
10. R. Tessier W. Burleson Reconfigurable computing and digital signal processing: a survey. Journal of VLSI Signal Processing 28 2001 1-2 7 27
11. A. Lodi andrea.lodi@deis.unibo.it M. Toma mtoma@deis.unibo.it F. Campi fcampi@deis.unibo.it A pipelined configurable gate array for embedded processors. Proceedings of ACM/SIGDA 11th International Symposium on Field-Programmable Gate Arrays (FPGA '03) Monterey, Calif, USA 2003 21 29
12. G. K. Rauwerda G. J. M. Smit P. M. Heysters Implementation of multi-standard wireless communication receivers in a heterogeneous reconfigurable system-on-chip. Proceedings of the 16th ProRISC Workshop Veldhoven, The Netherlands 2005 421 427
13. I. Kuon J. Rose Measuring the gap between FPGAs and ASICs. Proceedings of the ACM/SIGDA 14th International Symposium on Field-Programmable Gate Arrays (FPGA '06) Monterey, Calif, USA 2006 21 30
14. P. A. Laplante Computing requirements for self-repairing space systems. Journal of Aerospace Computing, Information and Communication 2 3 2005 154 169
15. T. Branca How to Add Features and Fix Bugs - Remotely. Here's What You Need to Consider When Designing a Xilinx Online Application. Xilinx, 2001
16. C. F. Da Silva christian_fsilva@yahoo.com.br A. M. Tokarnia tokarnia@dca.fee.unicamp.br RECASTER: synthesis of fault-tolerant embedded systems based on dynamically reconfigurable FPGAs. Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS '04) Santa Fe, NM, USA 2004 2003 2008
17. J. Rose A. El Gamal A. Sangiovanni-Vincentelli Architecture of field-programmable gate arrays. Proceedings of the IEEE 81 7 1993 1013 1029
18. W. H. Mangione-Smith billms@ucla.edu B. Hutchings D. Andrews Seeking solutions in configurable computing. IEEE Computer 30 12 1997 38 43
19. S. Hauck The roles of FPGAs in reprogrammable systems. Proceedings of the IEEE 86 1998 4 615 638
20. R. Hartenstein Trends in reconfigurable logic and reconfigurable computing. Proceedings of the 9th IEEE International Conference on Electronics, Circuits, and Systems (ICECS '02) Dubrovnik, Croatia 2002 801 808
21. K. Compton kati@ece.northwestern.edu S. Hauck hauck@ee.washington.edu Reconfigurable computing: a survey of systems and software. ACM Computing Surveys 34 2 2002 171 210
22. T. J. Todman tjt97@doc.ic.ac.uk G. A. Constantinides S. J. E. Wilton O. Mencer W. Luk P. Y. K. Cheung Reconfigurable computing: architectures and design methods. IEE Proceedings: Computers and Digital Techniques 152 2 2005 193 207
23. N. Kafafi K. Bozman S. J. E. Wilton stevew@ece.ubc.ca Architectures and algorithms for synthesizable embedded programmable logic cores. Proceedings of ACM/SIGDA 11th International Symposium on Field-Programmable Gate Arrays (FPGA '03) Monterey, Calif, USA 2003 3 11
24. M. Luthra mluthra@cecs.uci.edu S. Gupta sumitg@cecs.uci.edu N. Dutt dutt@cecs.uci.edu R. Gupta gupta@cs.ucsd.edu A. Nicolau nicolau@cecs.uci.edu Interface synthesis using memory mapping for an FPGA platform. Proceedings of IEEE 21st International Conference on Computer Design: VLSI in Computers and Processors (ICCD '03) San Jose, Calif, USA 2003 140 145
25. T. Wong S. J. E. Wilton Placement and routing for non-rectangular embedded programmable logic cores in SoC design. IEEE International Conference on Field-Programmable Technology (FPT '04) 2004 65 72 Brisbane, Australia
26. L. Shannon P. Chow Simplifying the integration of processing elements in computing systems using a programmable controller. Proceedings of 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '05) Napa Valley, Calif, USA 2005 63 72
27. B. R. Quinton S. J. E. Wilton Post-silicon debug using programmable logic cores. Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT '05) Singapore, Republic of Singapore 2005 241 248
28. A. Alsolaim J. Becker M. Glesner J. Starzyk Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems. Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '00) Napa Valley, Calif, USA 2000 205 214
29. C. Dick chris.dick@xilinx.com F. Harris fred.harris@sdsu.edu FPGA implementation of an OFDM PHY. Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers 1 Pacific Grove, Calif, USA 2003 905 909
30. B. Mohebbi behzad@morphotech.com E. C. Filho ecf@morphotech.com R. Maestre rafael@morphotech.com M. Davies mdavies@morphotech.com F. J. Kurdahi kurdahi@uci.edu A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. Proceedings of 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Newport Beach, Calif, USA 2003 103 108
31. K. Sarrigeorgidis J. M. Rabaey Massively parallel wireless reconfigurable processor architecture and programming. Proceedings of 17th International Parallel and Distributed Processing Symposium (IPDPS '03) Nice, France 2003 170 177
32. C. Ebeling ebeling@cs.washington.edu C. Fisher fisher@cs.washington.edu G. Xing guanbin.xing@kaonsystems.com M. Shen H. Liu hliu@ee.washington.edu Implementing an OFDM receiver on the RaPiD reconfigurable architecture. IEEE Transactions on Computers 53 11 2004 1436 1448
33. G. K. Rauwerda g.k.rauwerda@utwente.nl P. M. Heysters p.m.heysters@utwente.nl G. J. M. Smit g.j.m.smit@utwente.nl Mapping wireless communication algorithms onto a reconfigurable architecture. Journal of Supercomputing 30 3 2004 263 282
34. A. Rudra FPGA-based applications for software radio. RF Design Magazine 2004 24 35
35. P. Ryser Software define radio with reconfigurable hardware and software: a framework for a TV broadcast receiver. Embedded Systems Conference San Francisco, Calif, USA 2005 http://www.xilinx.com/products/design_resources/ proc_central/resource/proc_central_resources.htm
36. Altera Inc. Altera Devices on the Cutting Edge of Medical Technology. 2000, http://www.altera.com/corporate/cust_successes/customer/cst-CTI_PET.html
37. S. Coric M. Leeser E. Miller M. Trepanier Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '02) Monterey, Calif, USA 2002 217 226
38. A. Johnson K. Mackenzie Pattern matching in reconfigurable logic for packet classification. Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '01) Atlanta, Ga, USA 2001 126 130
39. F. Braun J. Lockwood M. Waldvogel Protocol wrappers for layered network packet processing in reconfigurable hardware. IEEE Micro 22 1 2002 66 74
40. E. L. Horta J. W. Lockwood D. E. Taylor D. Parlour Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. Proceedings of the 39th Design Automation Conference New Orleans, La, USA 2002 343 348
41. Lattice Semiconductor Corporation Lattice Orca ORLI10G Datasheet. 2002
42. Z. K. Baker zbaker@halcyon.usc.edu V. K. Prasanna prasanna@ganges.usc.edu A methodology for synthesis of efficient intrusion detection systems on FPGAs. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04) 2004 Napa Valley, Calif, USA 135 144
43. F. Crowe francisc@rennes.ucc.ie A. Daly aland@rennes.ucc.ie T. Kerins timk@rennes.ucc.ie W. Marnane liam@rennes.ucc.ie Single-chip FPGA implementation of a cryptographic co-processor. Proceedings of the IEEE International Conference on Field-Programmable Technology Brisbane, Australia 2004 279 285
44. T. T.-O. Kwok Y.-K. Kwok On the design of a self-reconfigurable SoPC based cryptographic engine. Proceedings of 24th International Conference on Distributed Computing Systems Workshops (ICDCS '04) Tokyo, Japan 2004 876 881
45. R. Khasgiwale L. Krnan A. Perinkulam R. Tessier Reconfigurable data acquisition system for weather radar applications. Proceedings of 48th Midwest Symposium on Circuits and Systems (MWSCAS '05) Cincinnati, Ohio, USA 2005 822 825
46. C. Sanderson D. Shand FPGAs supplant processors and ASICs in advanced imaging applications. FPGA and Structured ASIC Journal 2005 http://www. fpgajournal.com/articles_2005/20050104_nallatech.htm
47. T. R. Rimmele Recent advances in solar adaptive optics. Advancements in Adaptive Optics Proceedings of SPIE Glasgow, Scotland, UK 5490 2004 34 46
48. T. Fry tom@tomfry.com S. Hauck hauck@ee.washington.edu SPIHT image compression on FPGAs. IEEE Transactions on Circuits and Systems for Video Technology 15 9 2005 1138 1147
49. R. O. Reynolds P. H. Smith L. S. Bell H. U. Keller Design of Mars lander cameras for Mars Pathfinder, Mars Surveyor '98 and Mars Surveyor '01. IEEE Transactions on Instrumentation and Measurement 50 1 2001 63 71
50. M. Kifle M. Andro Q. K. Tran G. Fujikawa P. P. Chu Toward a dynamically reconfigurable computing and communication system for small spacecraft. Proceedings of the 21st International Communication Satellite System Conference & Exhibit (ICSSC '03) Yokohama, Japan 2003
51. A. Stoica D. Keymeulen C.-S. Lazaro W.-T. Li K. Hayworth R. Tawel Toward on-board synthesis and adaptation of electronic functions: an evolvable hardware approach. Proceedings of IEEE Aerospace Applications Conference Aspen, Colo, USA 2 1999 351 357
52. J. W. Weingarten jan.weingarten@epfl.ch G. Gruener gabriel.gruener@csem. ch R. Siegwart A state-of-the-art 3D sensor for robot navigation. Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS '04) 3 2004 2155 2160 Sendai, Japan
53. W. J. MacLean An evaluation of the suitability of FPGAs for embedded vision systems. Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR '05) 3 San Diego, Calif, USA 2005 131 131
54. K. Parnell You can take it with you: on the road with Xilinx. Xcell Journal 2002 43
55. K. Parnell The changing face of automotive ECU design. Xcell Journal 2005 53
56. Drivven Programmable Logic IP Cores for FPGA and CPLD. http://www.drivven.com/ProgrammableLogicIPCores.htm, 2006
57. D. Desmet P. Avasare P. Coene Design of Cam-E-leon: a run-time reconfigurable web camera. Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation (SAMOS '02) LNCS 2268 Springer Berlin, Germany 2002 274 290
58. M. Leaser mel@ece.neu.edu S. Miller smiller@ece.neu.edu H. Yu hyu@ece.neu.edu Smart camera based on reconfigurable hardware enables diverse real-time applications. Proceedings of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04) Napa Valley, Calif, USA 2004 147 155
59. J.-Y. Mignolet S. Vernalde D. Verkest R. Lauwereins Enabling hardware-software multitasking on a reconfigurable computing platform for networked portable multimedia appliances. Proceedings of the International Conference on Engineering Reconfigurable Systems and Algorithms Las Vegas, Nev, USA 2002 116 122
60. K. M. Hou E. Yao X. W. Tu A reconfigurable and flexible parallel 3D vision system for a mobile robot. Proceedings of Computer Architectures for Machine Perception New Orleans, La, USA 1993 215 221
61. J. P. Durbano F. E. Ortiz J. R. Humphrey P. F. Curt D. W. Prather FPGA-based acceleration of the 3D finite-difference time-domain method. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04) Napa Valley, Calif, USA 2004 156 163
62. Elixent DFA1000 RISC Accelerator. Elixent Bristol, England 2002
63. K. Leijten-Nowak knowak@natlab.research.philips.com J. L. Van Meerbergen jef.van.meerbergen@philips.com An FPGA architecture with enhanced datapath functionality. Proceedings of ACM/SIGDA 11th International Symposium on Field-Programmable Gate Arrays (FPGA '03) Monterey, Calif, USA 2003 195 204
64. Silicon Hive Silicon Hive Technology Primer. Phillips Electronics NV, The Netherlands. 2003
65. A. G. Ye yeandy@eecg.utoronto.ca J. Rose jayar@eecg.utoronto.ca Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. IEEE International Conference on Field-Programmable Technology (FPT '04) 2004 129 136 Brisbane, Australia
66. J. M. Arnold S5: the architecture and development flow of a software configurable processor. Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT '05) Singapore, Republic of Singapore 2005 121 128
67. Altera Inc. Stratix II Device Handbook, Volume 1. Altera San Jose, Calif, USA 2005
68. Xilinx Inc. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet. Xilinx, San Jose, Calif, USA, 2005
69. Xilinx Inc. Virtex-4 Family Overview. Xilinx, San Jose, Calif, USA, 2004
70. S. Haynes A. Ferrari P. Cheung Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. Proceedings of the Custom Integrated Circuits Conference San Diego, Calif, USA 1999 191 194
71. S. Hauck T. Fry M. Hosler J. Kao The Chimaera reconfigurable functional unit. Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97) Napa Valley, Calif, USA 1997 87 96
72. V. Betz J. Rose A. Marquardt Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Boston, Mass, USA 1999
73. K.-I. Kum W. Sung Combined word-length optimization and high-level synthesis of digital signal processing systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 8 2001 921 930
74. G. A. Constantinides P. Y. K. Cheung W. Luk The multiple wordlength paradigm. Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '01) Rohnert Park, Calif, USA 2001 51 60
75. U. Malik K. So O. Diessel Resource-aware run-time elaboration of behavioural FPGA specifications. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '02) Hong Kong 2002 68 75
76. Z. Zhao M. Leeser Precision modeling of floating-point applications for variable bitwidth computing. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03) 2003 208 214 Las Vegas, Nev, USA
77. A. DeHon andre@cs.caltech.edu J. Adams M. DeLorimier Design patterns for reconfigurable computing. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04) Napa Valley, Calif, USA 2004 13 23
78. K. Han khan@ece.utexas.edu B. L. Evans bevans@ece.utexas.edu E. E. Swartzlander Jr. eswartzla@aol.com Data wordlength reduction for low-power signal processing software. IEEE Workshop on Signal Processing Systems (SIPS '04) Austin, Tex, USA 2004 343 348
79. J. Park P. C. Diniz pedro@isi.edu K. R. Shesha Shayee sraghuna@usc.edu Performance and area modeling of complete FPGA designs in the presence of loop transformations. IEEE Transactions on Computers 53 11 2004 1420 1435
80. M. L. Chang mark.chang@olin.edu S. Hauck Précis: a usercentric word-length optimization tool. IEEE Design and Test of Computers 22 4 2005 349 361
81. C. Morra J. Becker M. Ayala-Rincon R. Hartenstein FELIX: using rewriting-logic for generating functionally equivalent implementations. Proceedings of International Conference on Field-Programmable Logic and Applications Tampere, Finland 2005 25 30
82. J. Cong S. Xu Technology mapping for FPGAs with embedded memory blocks. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '98) 1998 Monterey, Calif, USA 179 188
83. S. J. E. Wilton Implementing logic in FPGA memory arrays: heterogeneous memory architectures. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '02) Napa Valley, Calif, USA 2002 142 147
84. R. Tessier V. Betz D. Neto T. Gopalsamy Power-aware RAM mapping for FPGA embedded memory blocks. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '06) Monterey, Calif, USA 2006 189 198
85. S. Choi seonilch@usc.edu R. Scrofano rscrofan@usc.edu V. K. Prasanna J.-W. Jang jjang@sogang.ac.kr Energy-efficient signal processing using FPGAs. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '03) Monterey, Calif, USA 2003 225 234
86. J. Ou S. Choi V. K. Prasanna Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application. Proceedings of 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '03) Napa Valley, Calif, USA 2003 241 250
87. A. Gayasen K. Lee N. Vijaykrishnan M. Kandemir M. J. Irwin T. Tuan A dual-vdd low power FPGA architecture. Proceedings of the 14th International Conference on Field-Programmable Logic and Applications (FPL '04) Leuven, Belgium 145 157 2004
88. F. Li Y. Lin L. He lhe@ee.ucla.edu J. Cong Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. Proceedings of ACM/SIGDA 12th International Symposium on Field-Programmable Gate Arrays (FPGA '04) Monterey, Calif, USA 12 2004 42 50
89. A. Rahman V. Polavarapuv Evaluation of low-leakage design techniques for field programmable gate arrays. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '04) Monterey, Calif, USA 12 2004 23 30
90. J. Lamoureux S. J. E. Wilton On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays. Journal of Low Power Electronics 1 2005 2 119 132
91. K. K. W. Poon karap@ece.ubc.ca S. J. E. Wilton stevew@ece.ubc.ca A. Yan ayan@ece.ubc.ca A detailed power model for field-programmable gate arrays. ACM Transactions on Design Automation of Electronic Systems 10 2 2005 279 302
92. A. DeHon R. Huang J. Wawrzynek Hardware-assisted fast routing. Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '02) Napa Valley, Calif, USA 2002 205 215
93. P. Maidee pongstor@ece.umn.edu C. Ababei ababei@ece.umn.edu K. Bazargan kia@ece.umn.edu Fast timing-driven partitioning-based placement for island style FPGAs. Proceedings of the 40th Design Automation Conference (DAC '03) Anaheim, Calif, USA 2003 598 603
94. M. G. Wrighton wrighton@cs.caltech.edu A. M. DeHon andre@cs.caltech.edu Hardware-assisted simulated annealing with application for fast FPGA placement. ACM/SIGDA 11th International Symposium on Field-Programmable Gate Arrays (FPGA '03) 2003 33 42 Monterey, Calif, USA
95. M. Handa mhanda@ececs.uc.edu R. Vemuri ranga@ececs.uc.edu Hardware assisted two dimensional ultra fast placement. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS '04) 18 Santa Fe, NM, USA 2004 1915 1922
96. S. Li songli@cs.washington.edu C. Ebeling ebelinsi@cs.washington.edu QuickRoute: a fast routing algorithm for pipelined architectures. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '04) Brisbane, Australia 2004 73 80
97. R. Lysecky F. Vahid S. X.-D. Tan A study of the scalability of on-chip routing for just-in-time FPGA compilation. Proceedings of 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '05) Napa Valley, Calif, USA 2005 57 62
98. M. Chu N. Weaver K. Sulimma A. DeHon J. Wawrzynek Object oriented circuit-generators in Java. Proceedings of the 6th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98) Napa Valley, Calif, USA 1998 158 166
99. A. Derbyshire W. Luk Compiling run-time parametrisable designs. Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT '02) Hong Kong 2002 44 51
100. W. Wolf Computers as Components: Principles of Embedded Computer Systems Design. Morgan Kaufmann San Francisco, Calif, USA 2000
101. F. Barat R. Lauwereins G. Deconinck Reconfigurable instruction set processors from a hardware/software perspective. IEEE Transactions on Software Engineering 28 9 2002 847 862
102. F. Razdan M. Smith A high-performance microarchitecture with hardware-programmable functional units. Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO '94) San Jose, Calif, USA 1994 172 180
103. R. D. Wittig P. Chow OneChip: an FPGA processor with reconfigurable logic. Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines 1996 126 135 Napa Valley, Calif, USA
104. J. E. Carrillo P. Chow The effect of reconfigurable units in superscalar processors. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '01) Monterrey, Calif, USA 2001 141 150
105. B. Mei S. Vernalde D. Verkest R. Lauwereins Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '04) Paris, France 2 2004 1224 1229
106. Altera Inc. Nios II Processor Reference Handbook. Altera San Jose, Calif, USA 2005
107. Xilinx Inc. MicroBlaze Processor Reference Guide. Xilinx, San Jose, Calif, USA, 2003
108. A. Lawrence A. Kay W. Luk T. Nomura I. Page Using reconfigurable hardware to speed up product development and performance. Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications (FPL '95) Oxford, UK 1995 111 118
109. J. M. Rabaey A. Abnous Y. Ichikawa K. Seno M. Wan Heterogeneous reconfigurable systems. IEEE Workshop on Signal Processing Systems, Design and Implementation (SiPS '97) Leicester, UK 1997 24 34
110. J. R. Hauser J. Wawrzynek Garp: a MIPS processor with a reconfigurable coprocessor. Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97) Napa Valley, Calif, USA 1997 12 21
111. H. Schmit D. Whelihan A. Tsai M. Moe B. Levine R. R. Taylor PipeRench: a virtualized programmable datapath in 0.18 Micron technology. Proceedings of the Custom Integrated Circuits Conference Orlando, Fla, USA 2002 63 66
112. M. Bocchi C. De Bartolomeis C. Mucci A XiRisc-based SoC for embedded DSP applications. Proceedings of the IEEE Custom Integrated Circuits Conference Orlando, Fla, USA 2004 595 598
113. R. B. Kujoth kujoth@crhc.uiuc.edu C.-W. Wang cwang12@crhc.uiuc.edu D. B. Gottlieb dgottlie@crhc.uiuc.edu J. J. Cook jjcook@crhc.uiuc.edu N. P. Carter npcarter@crhc.uiuc.edu A reconfigurable unit for a clustered programmable-reconfigurable processor. Proceedings of ACM/SIGDA 12th International Symposium on Field-Programmable Gate Arrays (FPGA '04) Monterey, Calif, USA 12 2004 200 209
114. Xilinx Inc. Virtex-II Platform FPGAs: Complete Data Sheet. Xilinx, San Jose, Calif, USA, 2004
115. Actel Corporation VariCore TM Embedded Programmable Gate Array Core ( EPGA TM) 0.18μm Family. Actel, Mountain View, Calif, USA, 2001
116. M2000 Press Release - May 15, 2002. M2000, Bièvres, France, 2002
117. K. Compton S. Hauck Totem: custom reconfigurable array generation. Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '01) Rohnert Park, Calif, USA 2001 111 119
118. STMicroelectronics STMicroelectronics Introduces New Member of SPEArTM Family of Configurable System-on-Chip ICs. Press Release, 2005, http://us.st.com/stonline/press/news/year2005/p1711p.htm
119. F. Yang fanyang@u-bourgogne.fr M. Paindavoine paindav@u-bourgogne.fr Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification. IEEE Transactions on Neural Networks 14 5 2003 1162 1175
120. P. Weaver F. Palma Using software-configurable processors in biometric applications. Industrial Embedded Systems Resource Guide 84 86 2005 http://www.industrial-embedded.com
121. V. George Z. Hui J. Rabaey The design of a low energy FPGA. Proceedings of the International Symposium on Low Power Electronics and Design San Diego, Calif, USA 1999 188 193
122. P. Heysters p.m.heysters@utwente.nl G. J. M. Smit E. Molenkamp Energy-efficiency of the MONTIUM reconfigurable tile processor. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04) Las Vegas, Nev, USA 2004 38 44
123. G. Asadi gasadi@ece.neu.edu M. B. Tahoori mtahoori@ece.neu.edu Soft error rate estimation and mitigation for SRAM-based FPGAs. Proceedings of the ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays (FPGA '05) Monterey, Calif, USA 2005 149 160
124. Xilinx Inc. EasyPath Devices Datasheet. Xilinx, San Jose, Calif, USA, 2005
125. N. Campregher P. Y. K. Cheung G. A. Constantindes M. Vasilko Yield enhancements of design-specific FPGAs. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '06) Monterey, Calif, USA 2006 93 100
126. L. Sterpone luca.sterpone@polito.it M. Violante massimo.violante@polito. it Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. IEEE Transactions on Nuclear Science 52 5 2005 1545 1549
127. P. Bernardi M. Sonza Reorda L. Sterpone M. Violante On the evaluation of SEU sensitiveness in SRAM-based FPGAs. Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS &04) 2004 Madeira Island, Portugal 115 120
128. A. Tiwari anurag.tiwari@sun.com K. A. Tomko ktomko@ececs.uc.edu Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction. IEEE Transactions on Reliability 54 3 2005 459 467
129. P. Graham M. Caffrey M. Wirthlin D. E. Johnson N. Rollins Reconfigurable computing in space: from current technology to reconfigurable systems-on-a-chip. Proceedings of the IEEE Aerospace Conference 5 Big Sky, Mont, USA 2003 2399 2410
130. K. Hasuko C. Fukunaga R. Ichimiya A remote control system for FPGA-embedded modules in radiation enviornments. IEEE Transactions on Nuclear Science 49 2002 2, part 1 501 506
131. J. Lach W. H. Mangione-Smith M. Potkonjak Efficiently supporting fault-tolerance in FPGAs. Proceedings of the ACM/SIGDA 6th International Symposium on Field-Programmable Gate Arrays (FPGA '98) Monterey, Calif, USA 1998 105 115
132. N. Mokhoff Infrastructure IP Seen Aiding SoC Yields. EE Times, July 2002
133. B. P. Dave N. K. Jha COFTA: hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance. IEEE Transactions on Computers 48 4 1999 417 441
134. J. W. S. Liu Real-Time Systems. Prentice-Hall Englewood Cliffs, NJ, USA 2000
135. F. Verdier J. Prevotet A. Benkhelifa D. Chillet S. Pillement Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. Proceedings of the European Workshop on Reconfigurable Communication Centric (ReCoSoC '05) Montpellier, France 2005
136. B. Griese E. Vonnahme M. Porrmann U. Ruckert Hardware support for dynamic reconfiguration in reconfigurable SoC architectures. Proceedings of the 14th International Conference on Field-Programmable Logic and Applications (FPL '04) Leuven, Belgium 2004 842 846
137. C. Steiger Christoph.Steiger@esa.int H. Walder walder@tik.ee.ethz.ch M. Platzner marco.platzner@computer.org Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Transactions on Computers 53 11 2004 1393 1407
138. K. Danne M. Platzner Periodic real-time scheduling for FPGA computers. Proceedings of the 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES '05) Hamburg, Germany 2005 117 127
139. P. Brisk A. Kaplan R. Kastner M. Sarrafzadeh Instruction generation and regularity extraction for reconfigurable processors. Proceedings of the International Conferences on Compilers Architectures and Synthesis of Embeded Systems (CASES '02) Grenoble, France 2002 262 269
140. S. Yehia sami.yehia@arm.com N. Clark ntclark@umich.edu S. Mahlke mahlke@umich.edu K. Flautner krisztian.flautner@arm.com Exploring the design space of LUT-based transparent accelerators. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '05) 2005 11 21 San Francisco, Calif, USA
141. P. Yu T. Mitra tulika@comp.nus.edu.sg Satisfying real-time constraints with custom instructions. Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS '05) 2005 166 171 New Jersey, NJ, USA
142. T. Kean Secure configuration of field programmable gate arrays. Proceedings of 11th International Conference on Field-Programmable Logic and Applications (FPL '01) Belfast, Northern Ireland, UK 2001 142 151
143. L. Bossuet lilian.bossuet@univ-ubs.fr G. Gogniat guy.gogniat@univ-ubs.fr W. Burleson burleson@ecs.umass.edu Dynamically configurable security for SRAM FPGA bitstreams. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS '04) Santa Fe, NM, USA 2004 1995 2002
144. Xilinx Inc. A. Telikepalli Is Your FPGA Design Secure? Xilinx, San Jose, Calif, USA, 2003
145. Altera Inc. FPGA Design Security Solution Using Max II Devices. Altera San Jose, Calif, USA 2004
146. C. R. Rupp M. Landguth T. Garverick The NAPA adaptive processing architecture. Proceedings of 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98) Napa Valley, Calif, USA 1998 28 37
147. K. Bazargan R. Kastner M. Sarrafzadeh Fast template placement for reconfigurable computing systems. IEEE Design and Test of Computers 17 1 2000 68 83
148. K. Compton Z. Li J. Cooley S. Knol S. Hauck Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 3 2002 209 220
149. U. Malik umalik@cse.unsw.edu.au O. Diessel odiessel@cse.unsw.edu.au On the placement and granularity of FPGA configurations. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '04) Brisbane, Australia 2004 161 168
150. G. Brebner Swappable logic unit: a paradigm for virtual hardware. Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97) Napa Valley, Calif, USA 1997 77 86
151. E. Caspi R. Huang Y. Markovskiy J. Yeh J. Wawrzynek A. DeHon A streaming multi-threaded model. Proceedings of the 3rd Workshop on Media and Stream Processors (MSP '01) Austin, Tex, USA 2001 21 28
152. Y. Markovskiy E. Caspi R. Huang Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. Proceedings of 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA '02) Monterey, Calif, USA 2002 196 205
153. V. Nollet nollet@imec.be J.-Y. Mignolet mignolet@imec.be T. A. Bartic bartic@imec.be D. Verkest S. Vernalde R. Lauwereins Hierarchical run-time reconfiguration managed by an operating system for reconfigurable systems.
154. Z. Li S. Hauck Configuration compression for virtex FPGAs. Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '01) Rohnert Park, Calif, USA 2001 147 159
155. Z. Li K. Compton S. Hauck Configuration caching techniques for FPGA. Proceedings of 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '00) Napa Valley, Calif, USA 2000
156. A. DeHon DPGA utilization and application. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '96) Monterey, Calif, USA 1996 115 121
157. S. Trimberger D. Carberry A. Johnson J. Wong A time-multiplexed FPGA. Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines 1997 22 28 Napa Valley, Calif, USA
158. Z. Li S. Hauck Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. Proceedings of 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA '02) Monterey, Calif, USA 2002 187 195
159. R. Maestre F. J. Kurdahi N. Bagherzadeh H. Singh R. Hermida M. Fernandez Kernel scheduling in reconfigurable computing. Proceedings of Design, Automation and Test in Europe Conference and Exhibition Munich, Germany 1999 90 96
160. K. M. Gajjala Purna D. Bhatia Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Transactions on Computers 48 6 1999 579 590
161. G. Brebner A virtual hardware operating system for the Xilinx XC6200. Proceedings of the 6th International Workshop on Field-Programmable Logic and Applications (FPL '96) Dermstadt, Germany 327 336 1996
162. J. Resano javier1@dacya.ucm.es D. Mozos D. Verkest F. Catthoor A reconfiguration manager for dynamically reconfigurable hardware. IEEE Design and Test of Computers 22 5 2005 452 460
163. A. Sudarsanam arvind.sudarsanam@asu.edu M. Srinivasan mayur.s@asu.edu S. Panchanathan panch@asu.edu Resource estimation and task scheduling for multithreaded reconfigurable architectures. Proceedings of the International Conference on Parallel and Distributed Systems (ICPADS '04) Newport Beach, Calif, USA 2004 323 330
164. O. Diessel H. ElGindy M. Middendorf H. Schmeck B. Schmidt Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proceedings: Computers and Digital Techniques 147 3 2000 181 188
165. H. Quinn L. A. S. King M. Leeser W. Meleis Runtime assignment of reconfigurable hardware components for image processing pipelines. 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '03) Napa Valley, Calif, USA 2003 173 182
166. G. Stitt R. Lysecky F. Vahid Dynamic hardware/software partitioning: a first approach. Proceedings of the 40th Design Automation Conference (DAC '03) Anaheim, Calif, USA 2003 250 255
167. J. Noguera R. Badia Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. ACM Transactions on Embedded Computing Systems 3 2004 2 385 406
168. A. Ahmadinia ahmadinia@cs.fau.de C. Bobda bobda@cs.fau.de D. Koch dirk.koch@cs.fau.de M. Majer mateusz@cs.fau.de J. Teich teich@cs.fau.de Task scheduling for heterogeneous reconfigurable computers. Proceedings of the 17th Symposium on Integrated Cicuits and Systems Design Pernambuco, Brazil 2004 22 27
169. R. Lysecky rlysecky@cs.ucr.edu F. Vahid vahid@cs.ucr.edu A configurable logic architecture for dynamic hardware/software partitioning. Proceedings of Design, Automation and Test in Europe Conference and Exhibition Paris, France 1 2004 480 485
170. W. Fu K. Compton An execution environment for reconfigurable computing. Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '05) Napa Valley, Calif, USA 2005 149 158
171. T. Wiangtong P. Y. K. Cheung W. Luk Hardware/software codesign: a systematic approach targeting data-intensive applications. IEEE Signal Processing Magazine 22 3 2005 14 22
172. P. Benoit L. Torres G. Sassatelli M. Robert G. Cambon Automatic task scheduling / loop unrolling using dedicated RTR controllers in coarse grain reconfigurable architectures. Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS '05) Denver, Colo, USA 2005 148a
173. H. Simmler L Levison R. Manner Multitasking on FPGA coprocessors. The International Conference on Field-Programmable Logic, Reconfigurable Computing, and Applications (FPL '00) Villach, Austria 2000 121 130
174. H. Kalte M. Porrmann Context saving and restoring for multitasking in reconfigurable systems. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '05) Tampere, Finland 2005 223 228
175. Y. Li T. Callahan E. Darnell R. Harr U. Kurkure J. Stockwood Hardware-software co-design of embedded reconfigurable architectures. Proceedings of 37th Design Automation Conference (DAC '00) Los Angeles, Calif, USA 2000 507 512
176. M. J. W. Savage Z. Salcic G. Coghill G. Covic Extended genetic algorithm for codesign optimization of DSP systems in FPGAs. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '04) Brisbane, Australia 2004 291 294
177. S. Kumar J. H. Aylor B. W. Johnson W. A. Wulf The Codesign of Embedded Systems: A Unified Hardware/Software Representation. Springer New York, NY, USA 1995
178. M. Chiodo P. Giusto A. Jurecska H. C. Hsieh A. Sangiovanni-Vincentelli L. Lavagno Hardware-software codesign of embedded systems. IEEE Micro 14 4 1994 26 36
179. R. Ernst ernst@ida.ing.tu-bs.de Codesign of embedded systems: status and trends. IEEE Design and Test of Computers 15 2 1998 45 54
180. W. Wolf wolf@ee.princeton.edu A decade of hardware/software codesign. IEEE Computer 36 4 2003 38 43
181. M. Gokhale J. M. Stone J. Arnold M. Kalinowski Stream-oriented FPGA computing in the Streams-C high level language. Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '00) Napa Valley, Calif, USA 2000
182. Synopsys Inc. CoCentric System C Compiler. Synopsys, Mountain View, Calif, USA, 2000
183. M. Weinhardt W. Luk Pipeline vectorization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 2 2001 234 248
184. D. Niehaus D. Andrews Using the multi-threaded computation model as a unifying framework for hardware-software co-design and implementation. Proceedings of the 9th International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS '03) Capri, Italy 2003 317
185. B. Swahn swahn@ece.tufts.edu S. Hassoun soha@cs.tufts.edu Hardware scheduling for dynamic adaptability using external profiling and hardware threading. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '03) 2003 58 64 San Jose, Calif, USA
186. G. De Micheli Hardware synthesis from C/C++ models. Proceedings of Design, Automation and Test in Europe Conference and Exhibition Munich, Germany 1999 382 383
187. A. DeHon Very large scale spatial computing. Proceedings of the 3rd International Conference on Unconventional Models of Computation (UMC '02) Kobe, Japan 2002 27 37
188. D. Andrews dandrews@ittc.ku.edu D. Niehaus niehaus@ittc.ku.edu P. Ashenden peter@ashenden.com.au Programming models for hybrid CPU/FPGA chips. IEEE Computer 37 1 2004 118 120
189. J.-P. David J.-D. Legat A data-flow oriented co-design for reconfigurable systems. Proceedings of the 9th International Workshop on Rapid System Prototyping Leuven, Belgium 1998 207 211
190. R. Rinker M. Carter A. Patel An automated process for compiling dataflow graphics into reconfigurable hardware. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 1 2001 130 139
191. B. Mei S. Vernalde D. Verkest H. De Man R. Lauwereins DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '02) Hong Kong 2002 166 173
192. J. M. P. Cardoso jmpc@acm.org On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures. IEEE Transactions on Computers 52 10 2003 1362 1375
193. S. Banerjee banerjee@ics.uci.edu E. Bozorgzadeh eli@ics.uci.edu N. Dutt dutt@ics.uci.edu Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. Proceedings of the 42nd Design Automation Conference (DAC '05) Anaheim, Calif, USA 2005 335 340
194. C. Bobda A. Ahmadinia Dynamic interconnection of reconfigurable modules on reconfigurable devices. IEEE Design and Test of Computers 22 5 2005 443 451
195. B. Hutchings B. Nelson Developing and debugging FPGA applications in hardware with JHDL. Proceedings of 33rd Asilomar Conference on Signals, Systems and Computers Pacific Grove, Calif, USA 1 1999 554 558
196. K. A. Tomko A. Tiwari Hardware/software co-debugging for reconfigurable computing. Proceedings of the 5th IEEE International High-Level Design, Validation, and Test Workshop (HLDVT '00) Berkeley, Calif, USA 2000 59 63
197. T. Rissa tpr@doc.ic.ac.uk W. Luk w.luk@doc.ic.ac.uk P. Y. K. Cheung p.cheung@imperial.ac.uk Automated combination of simulation and hardware prototyping. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04) Las Vegas, Nev, USA 2004 184 193
198. G. Talavera Guillermo.Talavera@uab.es V. Nollet J.-Y. Mignolet Hardware-software debugging techniques for reconfigurable systems-on-chip. Proceedings of the IEEE International Conference on Industrial Technology (ICIT '04) 3 2004 1402 1407 Hammamet, Tunisia
199. Y. Jin yujia@eecs.berkeley.edu N. Satish nrsatish@eecs.berkeley.edu K. Ravindran kaushikr@eecs.berkeley.edu K. Keutzer keutzer@eecs.berkeley.edu An automated exploration framework for FPGA-based soft multiprocessor systems. Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '05) Jersey City, NJ, USA 2005 273 278
200. P. Yiannacouras J. G. Steffan J. Rose Application-specific customization of soft processor microarchitecture. Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '06) Monterey, Calif, USA 2006 201 210
201. R. E. Gonzalez ricardog@tensilica.com Xtensa: a configurable and extensible processor. IEEE Micro 20 2 2000 60 70
202. A. Yan ayan@ece.ubc.ca S. J. E. Wilton stevew@ece.ubc.ca Sequential synthesizable embedded programmable logic cores for system-on-chip. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '04) 2004 435 438 Orlando, Fla, USA
203. S. Hauck K. Compton K. Eguro M. Holland S. Philips A. Sharma Totem: domain-specific reconfigurable logic. to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
204. I. Kuon ikuon@eecg.utoronto.ca A. Egier aegier@eecg.utoronto.ca J. Rose jayar@eecg.utoronto.ca Design, layout and verification of an FPGA using automated tools. Proceedings of the ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays (FPGA '05) Monterey, Calif, USA 2005 215 226