Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

IEEE Transactions on Device and Materials Reliability

Volumn 6, Issue 1, 2006, Pages 95-99

  Chung, Steve S ^a,b,d,e,f   Yeh, Chang Hua ^c,g   Feng, Hsin Jung ^b   Lai, Chao Sung ^c,g   Yang, Jiuun Jer ^c,h   Chen, Chi Chun ^d   Jin, Ying ^d   Chen, Shih Chang ^d   Liang, Mong Song ^a,d,i  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c CHANG GUNG UNIVERSITY   (Taiwan)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^e UMC Research   (Taiwan)

^f UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^g NANYA TECHNOLOGY CORPORATION   (Taiwan)

^h SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION   (China)

ⁱ Advanced Module Technology Division

Author keywords

Atomic layer deposition (ALD); Gate stack; Narrow width effect; Negative bias temperature instability (NBTI); Shallow trench isolation (STI)

Indexed keywords

ATOMIC LAYER DEPOSITION; GATE STACK; NARROW-WIDTH EFFECT; NEGATIVE BIAS TEMPERATURE INSTABILITY; SHALLOW TRENCH ISOLATION;

HYDROGEN; INTERFACES (MATERIALS); PLASMA DEVICES; RELIABILITY; STRESSES; SYSTEM STABILITY; TEMPERATURE;

MOSFET DEVICES;

EID: 33645803830     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2006.871415     Document Type: Article

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