A formal model of clock domain crossing and automated verification of time-triggered hardware

Proceedings - Formal Methods in Computer Aided Design, FMCAD 2007

Volumn , Issue , 2007, Pages 223-230

  Schmaltz, Julien ^a  

^a RADBOUD UNIVERSITY NIJMEGEN   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CLOCKS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; DIGITAL ARITHMETIC; DIGITAL TO ANALOG CONVERSION; MODEL CHECKING; SECURITY OF DATA; SEPARATION; STANDARDS;

ASYNCHRONOUS TRANSMISSIONS; AUTOMATED VERIFICATION; BIT CLOCK; FLEXRAY; FORMAL MODELING; ISABELLE/HOL; META STABILITY; MODEL CHECKERS; STATE TRANSITIONS; SYNCHRONIZATION ALGORITHMS;

FORMAL METHODS;

EID: 47249161096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FAMCAD.2007.22     Document Type: Conference Paper

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