A formal model of lower system layers

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2006

Volumn , Issue , 2006, Pages 191-192

  Schmaltz, Julien ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; DATA TRANSFER; DIGITAL CIRCUITS; LOGIC CIRCUITS;

ARBITRARY CLOCK PERIODS; BIT TRANSMISSION; DIGITAL MODELS; REGISTERS;

FORMAL METHODS;

EID: 34547464258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FMCAD.2006.1     Document Type: Conference Paper

References (3)

1. G.M. Brown and L. Pike, Easy Parameterized Verification of Biphase Mark and 8N1 Protocols, TACAS'06, Springer, 2006.
2. T. Nipkow, L.C. Paulson and M. Wenzel, Isabelle/HOL: A Proof Assistant for Higher-Order Logic, Vol. 2283 of LNCS, Springer, 2002.
3. S. Beyer et al., Towards the Formal Verification of Lower System Layers in Automotive Systems, ICCD 2005.