Getting formal verification into design flow

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5014 LNCS, Issue , 2008, Pages 12-32

  Arvind, ^a   Dave, Nirav ^a   Katelman, Michael ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH LEVEL LANGUAGES; LINGUISTICS; QUERY LANGUAGES;

CONCRETE DESIGNS; DEBUGGING AIDS; DESIGN FLOWS; ENGINEERING PRACTICES; FOREIGN LANGUAGES; FORMAL TECHNIQUES; FORMAL TOOLS; FORMAL VERIFICATIONS; HARDWARE ENGINEERS; HEIDELBERG (CO); HIGH LEVEL DESIGNS; INTERNATIONAL SYMPOSIUM;

FORMAL METHODS;

EID: 47249121781     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-68237-0_2     Document Type: Conference Paper

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