Automatic synthesis of cache-coherence protocol processors using bluespec

Proceedings - Third ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'05

Volumn 2005, Issue , 2005, Pages 25-34

  Dave, Nirav ^a   Ng, Man Cheuk ^a   Arvind, ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACT PROTOCOLS; ATOMIC ACTIONS; HIGH-LEVEL ABSTRACT DESCRIPTIONS; NON-BLOCKING MSI CACHE-COHERENCE PROTOCOL;

ABSTRACTING; BUFFER STORAGE; COMPUTER HARDWARE; DISTRIBUTED COMPUTER SYSTEMS; NETWORK PROTOCOLS; PROBLEM SOLVING;

MICROCONTROLLERS;

EID: 33745164924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2005.1487887     Document Type: Conference Paper

References (17)

1. Homayoon Akhiani, Damien Doligez, Paul Harter, Leslie Lamport, Mark Tuttle, and Yuan Yu. Cache-Coherence Verification with TLA+. In World Congress on Formal Methods in the Development of Computing Systems, Industrial Panel, Toulouse, France, Sept, 1999.
2. C. Amza, A. L. Cox, S. Dwarkadas, L-J. Jin, K. Rajamani, and W. Zwaenepoel. Adaptive protocols for software distributed shared memory. Proc. of the IEEE, Special Issue on Distributed Shared Memory, 87(3):467-475, 1999.
3. Bluespec, Inc., Waltham, MA. Bluespec SystemVerilog Version 3.8 Reference Guide, November 2004.
4. Satish Chandra, Brad Richards, and James R. Larus. Teapot: Language support for writing memory coherence protocols. In PLDI, pages 237-248, 1996.
5. D. Culler, J. P. Singh, and A. Gupta. Modern Parallel Computer Architecture. Morgan Kaufmann, 1997.
6. Nirav Dave. Designing a Processor in Bluespec. Master's thesis, Electrical Engineering & Computer Science Dept., MIT, Cambridge, MA, Jan 2005.
7. Babak Falsafi and David A. Wood. Reactive numa: A design for unifying s-coma and cc-numa. In Proceedings of the 24th Annual International Symposium on Computer Architecture, June 1997.
8. James C. Hoe and Arvind. Operation-Centric Hardware Description and Synthesis. IEEE TRANSACTIONS on Computer-Aided Design of Integrated Circuits and Systems, 23(9), September 2004.
9. D. E. Lenoski. The Design and Analysis of DASH A Scalable Directorybased Multiprocessor. PhD thesis, Stanford University, Stanford, CA, 1992.
10. Ratan Nalumasu and Ganesh Gopalakrishnan. Deriving efficient cache coherence protocols through refi nement. In Formal Methods for Parallel Programming: Theory and Applications (FMPPTA), Orlando, FL, 98.
11. Seungjoon Park and David L. Dill. Protocol verification by aggregation of distributed transactions. In CAV '96: Proceedings of the 8th International Conference on Computer Aided Verification, pages 300-310, London, UK, 1996. Springer-Verlag.
12. F. Pong and M. Dubois. A New Approach for the Verification of Cache Coherence Protocols. IEEE Transactions on Parallel and Distributed Systems, August 1995.
13. Daniel L. Rosenband and Arvind. Modular Scheduling of Guarded Atomic Actions. In Proceedings of DAC'04, San Diego, CA, 2004.
14. Xiaowei Shen. Design and Verification of Adaptive Cache Coherence Protocols. PhD thesis, Electrical Engineering & Computer Science Dept., MIT, Cambridge, MA, 2000.
15. Xiaowei Shen and Arvind. Specification of Memory Models and Design of Provably Correct Cache Coherence Protocols. In MIT CSAIL CSG Technical Memo 398 (http://csg.csail.mit.edu/pubs/memos/Memo-398/memo398.pdf), January 1997.
16. Joseph E. Stoy, Xiaowei Shen, and Arvind. Proofs of Correctness of Cache-Coherence Protocols. In Proceedings of FME'01: Formal Methods for increasing Software Productivity, pages 47-71, London, UK, 2001. Springer-Verlag.
17. Xiaowei Shen, Arvind, Larry Rudolph. CACHET: An Adaptive Cache Coherence Protocol for Distributed Shared-Memory Systems. In Proceedings of the 13th ACM SIGARCH International Conference on Supercomputing, Rhodes, Greeces, Jan 1999.