Investigation of thermal crosstalk between SOI FETs by the subthreshold sensing technique

IEEE Transactions on Electron Devices

Volumn 55, Issue 7, 2008, Pages 1733-1740

  Shamsa, Manu ^a   Solomon, Paul M ^b   Jenkins, Keith A ^b   Balandin, Alexander A ^a,c   Haensch, Wilfried ^b  

^a University of California Riverside   (United States)

^b INTEL CORPORATION   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Heating; MOSFET; Pulse probe; Silicon oninsulator (SOI); Transient

Indexed keywords

CROSSTALK; FINITE ELEMENT METHOD; LINEAR EQUATIONS; PHOTOACOUSTIC EFFECT; RADIO; SEMICONDUCTOR DOPING; SENSORS; TRANSISTORS;

(P ,P ,T) MEASUREMENTS; DEVICE PERFORMANCES; DEVICE STRUCTURES; ELECTRICAL PULSES; FIELD EFFECT TRANSISTOR (FET); FINITE ELEMENT METHOD (FEM); HEAT DIFFUSION EQUATIONS; HEAT DIFFUSIONS; HIGH RESOLUTIONS; HIGH SPEEDS; INTERFACE QUALITY; LAYER THICKNESSES; LOCAL TEMPERATURES; MATERIAL SELECTIONS; PROBE SAMPLING; SENSING TECHNIQUES; SILICON ON INSULATOR (SOI) SUBSTRATES; SIMULATION APPROACH; SUB THRESHOLD CURRENT; SUB THRESHOLDS; TEMPERATURE PROFILING; TEMPERATURE RESOLUTION; TEMPERATURE SENSITIVITIES; TIME RESOLUTIONS;

FIELD EFFECT TRANSISTORS;

EID: 46649107312     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.925162     Document Type: Article

References (20)

1. H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, "Nanoscale CMOS," Proc. IEEE, vol. 87, no. 4, pp. 537-570, Apr. 1999.
2. C.-T. Chuang, K. Bernstein, R. V. Joshi, R. Puri, K. Kim, E. J. Nowark, T. Ludwig, and I. Aller, "Scaling planar silicon devices," IEEE Circuits Devices Mag., vol. 4, no. 1, pp. 6-19, Jan. 2004.
3. A. Amerasekra and J. Verwey, "ESD in integrated circuits," Qual. Reliab. Eng. Int., vol. 8, pp. 259-272, Feb. 1992.
4. M. Chan, S. S. Yuen, Z.-J. Ma, K. Hui, P. K. Ko, and C. Ju, "Comparison of ESD protection capability of SOI and bulk CMOS output buffers," in Proc. IEEE Int. Reliab. Phys. Symp., 1994, pp. 292-308.
5. R. V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, C. T. Chuang, and J. A. Pascular-Gitierrez, "Direct temperature measurement for VLSI circuits and 3D modeling of self-heating in sub-0.13 μm SOI technologies," in Proc. 18th Int. Conf. VLSI Des., 2005, pp. 697-702.
6. M. B. Ketchen, K. Xiu, and M. Bhushan, "Measurement of thermal time constant in 65-nm PD-SOI technology with sub-ns resolution," in Proc. Int. Conf. SOI, Oct. 2-4, 2007, pp. 53-54.
7. K. A. Jenkins, J. Y.-C. Sun, and J. Gautier, "Characteristics of SOI FETs under pulsed conditions," IEEE Trans. Electron Devices, vol. 44, no. 11, pp. 1923-1930, Nov. 1997.
8. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, p. 128.
9. B. M. Tenbroek, W.-R. White, M. S. L. Lee, R. J. T. Bunyan, M. J. Uren, and K. M. Brunson, "Characterization of layout dependent thermal coupling in SOI CMOS current mirrors," IEEE J. Solid-State Circuits vol. 43, no. 12, pp. 1037-1046, Dec. 1998.
10. L. J. McDaid, S. Hall, P. H. Mellor, W. Eccleston, and J. C. Alderman, "Physical origin of negative differential resistance in SOI transistors," Electron. Lett., vol. 25, no. 13, pp. 827-828, Jun. 1989.
11. O. Le Neel and M. Haond, "Electrical transient study of negative resistance in SOI MOS transistors," Electron. Lett., vol. 26, no. 1, pp. 73-74, Jan. 1990.
12. K. Filippov and A. A. Balandin, "The effect of the thermal boundary resistance on self-heating of A1GaN/GaN HFETs," J. Nitride Semicond. Res., vol. 8, no. 4, pp. 4-1-4-3, 2003.
13. E. Pop, S. Sinha, and K. E. Goodson, "Heat generation and transport in nanometer-scale transistors," in Proc. IEEE, Aug. 2006, vol. 94, pp. 1587-1601.
14. V. O. Turin and A. A. Balandin, "Electro-thermal simulations of the self-heating effects in GaN-based field-effect transistors," J. Appl. Phys., vol. 100, no. 5, pp. 054 501-1-054 501-8, Sep. 2006.
15. W. Liu and M. Asheghi, "Thermal conduction in ultrathin pure and doped single-crystal silicon layers at high temperature," J. Appl. Phys. vol. 98, no. 12, pp. 123 523-1-123 523-6, Dec. 2005.
16. Y. S. Ju and K. E. Goodson, "Phonon scattering in silicon films with thickness of order 100 nm," Appl. Phys. Lett., vol. 74, no. 20, pp. 3005-3007, May 1999.
17. H.-K. Lyeo and D. G. Cahill, "Thermal conductance of interfaces between highly dissimilar materials," Phys. Rev. B, Condens. Matter, vol. 73, no. 14, pp. 144 301-1-144 301-6, Apr. 2006.
18. A. A. Balandin and K. L. Wang, "Significant decrease of the lattice thermal conductivity due to phonon confinement in a free-standing semi-conducting quantum well," Phys. Rev. B, Condens. Matter, vol. 58, no. 3, pp. 1544-1549, Jul. 1998.
19. T. Zeng and G. Chen, "Phonon heat conduction in thin films: Impacts of thermal boundary resistance and internal heat generation," J. Heat Transf., vol. 123, no. 2, pp. 340-347, Apr. 2001.
20. E. T. Swartz and R. O. Pohl, "Thermal boundary resistance," Rev. Mod. Phys., vol. 61, no. 3, pp. 605-668, Jul. 1989.