A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 1, 2004, Pages 196-200

  Starzyk, Janusz A ^a   Mohn, Russell P ^b   Jing, Liang ^a  

^a US Institute of Navigation   (United States)

^b SARNOFF CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; SEQUENTIAL SWITCHING; SYSTEMATIC ERRORS;

CMOS MACROCELL; SWITCHING ALGORITHM; SYSTEMATIC ERROR REDUCTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 4644324790     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.821282     Document Type: Article

References (10)

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