Low complexity implementations of sum-product algorithm for decoding low-density parity-check codes

2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Volumn , Issue , 2006, Pages 262-267

  Oh, Dacsun ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; BOOLEAN FUNCTIONS; CODES (STANDARDS); CODES (SYMBOLS); COMPUTATIONAL METHODS; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA COMPRESSION; DECODING; FUNCTION EVALUATION; HARDWARE; ONTOLOGY; REDUCTION; SIGNAL PROCESSING; STATISTICAL PROCESS CONTROL; STORAGE (MATERIALS); SULFATE MINERALS; TABLE LOOKUP; TRANSCEIVERS;

COMPRESSION TECHNIQUES; DECODER ARCHITECTURE; DECODING PERFORMANCE; FINITE PRECISION; HARDWARE COMPLEXITIES; HARDWARE IMPLEMENTATIONS; LOOK UP TABLE (LUT); LOW DENSITY PARITY-CHECK (LDPC) CODES; LOW-COMPLEXITY; NON LINEAR FUNCTIONS; PERFORMANCE LOSSES; QUANTIZATION SCHEMES; SIGNAL PROCESSING SYSTEMS; SIMULATION RESULTS; SUM-PRODUCT ALGORITHM (SPA); TWO TYPES; UNIFORM QUANTIZATION; WORD LENGTHS;

DATA STORAGE EQUIPMENT;

EID: 46249109884     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2006.352592     Document Type: Conference Paper

References (17)

1. R. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: MIT Press, 1963.
2. D.J.C. MacKay, "Good codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 3, pp. 399-431, Mar. 1999.
3. A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
4. M. Rovini, N.E. L'Insalata, F. Rossi, and L. Fanucci, "VLSI design of a high-throughput multi-rate decoder for structured LDPC codes Rovini," in Proc. 8th Euromicro Conf. on Digital System Design, pp. 202-209, Aug. 2005.
5. J. Lu, J.M.F. Moura, "Structured LDPC codes for high-density recording: large girth and low error floor," IEEE Trans. Magnetics, vol. 42, No. 2, pp. 208-213, Feb. 2006.
6. M. Mansour and N.R. Shanbhag, "High-throughput LDPC decoders," IEEE Trans. 11SI Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003.
7. H. Zhong and T. Zhang, "Block-LDPC: A Practical LDPC Coding System Design Approach," IEEE Trans. Circuits Syst. I. vol. 52, no. 4, pp. 766-775, Apr. 2005.
8. Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications, Draft EN 302 307 V1.1.1 ed., ETSI, June 2004.
9. "IEEE P802.11 Wireless LANs TGnSync Proposal: TGnSync Proposal Technical Specification," May 2005, IEEE 11-04-0889-06-000n.
10. "IEEE P802.11 Wireless LANs WWiSE Proposal: High throughout extension to the 802.11 Standard," Aug. 2004. IEEE 11-04-0886-00-000n.
11. "LDPC coding for OFDMA PHY," 802.16REVe Sponsor Ballot Recirculation comment, Jul. 2004, IEEE C802.16e-04/141r2.
12. T. Zhang, Z. Wang, and K.K. Parhi, "On finite precision implementation of low density parity check codes decoder," in Proc. IEEE Int. Symp. Circuits Syst., vol. 4, pp. 202-205, May 2001.
13. S.L. Howard, V.C. Gaudet, and C. Schlegel, "Soft-bit decoding of regular low-density parity-check codes," IEEE Trans. Circuits and Systems II, vol. 52", no. 10, pp. 646-650, Oct. 2005.
14. G. Masera, F. Quaglio, and F. Vacca, "Finite precision implementation of LDPC decoders." IEE Proc. Comms., vol. 152, no. 6, pp. 1098-1102, Dec. 2005.
15. D. Oh and K.K. Parhi, "Modified sum-product decoding algorithm for irregular low-density parity-check codes," submitted in IEEE Trans. on Circuit and Systems II, Aug. 2006.
16. H. Sankar and K.R. Narayanan, "Memory-efficient sum-product decoding of LDPC codes," IEEE Trans. on Comms., vol. 52, no. 8, pp, 1225-1230, Aug. 2004.
17. Z. Wang, Y. Chen, and K.K. Parhi, "Area efficient decoding of quasicyclic low density parity check codes," in IEEE Proc. ICASSP '04, vol. 5, pp. 49-52, May 2004.