A multi-context pipelined array for embedded systems

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 581-588

  Lodi, Andrea ^a   Mucci, Claudio ^a   Bocchi, Massimo ^a   Cappelli, Andrea ^a   De Dominicis, Mario ^a   Ciccarelli, Luca ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; DYNAMIC MODELS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUITS; LOGIC DEVICES; MOTION PICTURE EXPERTS GROUP STANDARDS; OPTICAL DESIGN; PROGRAM PROCESSORS;

ARCHITECTURAL CHOICES; AREA OVERHEAD; CMOS TECHNOLOGIES; COMPLEX SOCS; COMPUTATIONAL DENSITY; CONTROL UNIT (CU); DATA PATHS; DYNAMIC RECONFIGURATIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA) DESIGN; FIELD PROGRAMMABLE LOGIC (FPL); HARDWARE SUPPORTS; HIGH-LEVEL LANGUAGE (HLL); INTERNATIONAL CONFERENCES; LOGIC CELLS; RE-CONFIGURABLE; RECONFIGURABLE DEVICES; VIRTEX II;

COMPUTATIONAL EFFICIENCY;

EID: 46249102696     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311270     Document Type: Conference Paper

References (15)

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