Decoder-based interconnect structure for multi-context FPGAs

Electronics Letters

Volumn 39, Issue 4, 2003, Pages 362-364

  Lodi, A ^a   Ciccarelli, L ^a   Cappelli, A ^a   Campi, F ^a   Toma, M ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DECODING; TOPOLOGY; TRANSISTORS;

INTERCONNECT STRUCTURES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0037456329     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030204     Document Type: Article

References (4)

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2. DEHON, A.: 'DPGA-coupled microprocessors: commodity ICs for the early 21st century'. Proc. IEEE Symp. on FCCM, Napa Valley, CA, USA, April 1994, pp. 31-39
3. TRIMBERGER, S., CARBERRY, D., JHONSON, A., and WONG, J.: 'A time multiplexed FPGA'. Proc. IEEE Symp. on FCCM, Napa Valley, CA, USA, April 1997, pp. 34-40
4. BAENA-LECUYER, V., AGUIRRE, M., TORRALBA, A., FRANQUELO, L., and FAURA, J.: 'Decoder-driven switching matrices in multicontext fpgas: area reduction and their effect on routability'. Proc. IEEE ISCAS'99, Orlando, FL, USA, 1999, Vol. 1, pp, 463-466