Tunable highly linear floating-gate CMOS resistor using common-mode linearization technique

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 4, 2008, Pages 999-1010

  Özalevli, Erhan ^a,b   Hasler, Paul E ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

CMOS; Floating gate; Resistor; Tunable

Indexed keywords

CMOS INTEGRATED CIRCUITS; HARMONIC DISTORTION; LINEARIZATION; TRANSISTORS;

COMMON-MODE LINEARIZATION TECHNIQUE; FLOATING-GATE TRANSISTORS; FOWLER-NORDHEIM TUNNELING;

RESISTORS;

EID: 44949156673     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.916459     Document Type: Article

References (34)

1. E. Özalevli and P. E. Hasler, "Programmable floating-gate CMOS resistors," in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 3, pp. 2168-2171.
2. E. Özalevli and P. E. Hasler, "Design of a CMOS floating-gate resistor for highly linear amplifier and multiplier applications," in Proc. IEEE Custom Integr. Circuits Conf., 2005, pp. 735-738.
3. S. Tantry, T. Yoneyama, and H. Asai, "Two floating resistor circuits and their applications to synaptic weights in analog neural networks," in Proc. Int. Symp. Circuits Syst., 2001, vol. 1, pp. 564-567.
4. Z. Czarnul and Y. P. Tsividis, "Implementation of MOSFET-C filters based on active RC prototypes," Electron. Lett., vol. 24, pp. 184-185, 1988.
5. Y. Tsividis, M. Banu, and J. Khoury, "Continuous-time MOSFET-C filters in VLSI," IEEE Trans. Circuits Syst., vol. CAS-33, no. 1, pp. 125-140, Jan. 1986.
6. S. Sakurai and M. Ismail, "A CMOS square-law programmable floating resistor independent of the threshold voltage," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 4, pp. 565-574, Apr. 1992.
7. S. P. Singh, J. V. Hansom, and J. Vlach, "A new floating resistor for CMOS technology," IEEE Trans. Circuits Syst., vol. 36, no. 11, pp. 1217-1220, Nov. 1989.
8. M. Kushima, K. Tanno, H. Kumagai, and O. Ishizuka, "Low-power and wide-input range voltage controlled linear variable resistor using an FG-MOSFET and its application," IEICE Trans. Fundam. Electron., Commun. Comput. Sci., pp. 342-349, 2003.
9. H. Youssef, R. Newcomb, and M. Zaghloul, "A CMOS voltage-controlled linear resistor with wide dynamic range," in Proc. 21st Southeastern Symp. Syst. Theory, 1989, pp. 681-683.
10. Z. Wang and W. Guggenbuhl, "A voltage controllable linear MOS transconductor using bias offset technique," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 315-317, Apr. 1990.
11. M. Banu and Y. Tsividis, "Fully integrated active RC filters in MOS technology," IEEE J. Solid-State Circuits, vol. SC-18, no. 3, pp. 644-651, Jun. 1983.
12. J. N. Babanezhad and G. C. Temes, "A linear nMOS depletion resistor and its application in an integrated amplifier," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 932-938, Dec. 1984.
13. Z. Czarnul, "Comments on a linear nMOS depletion resistor and its application in an integrated amplifier," IEEE J. Solid-State Circuits, vol. SC-22, no. 1, pp. 124-127, Feb. 1987.
14. G. Wilson and P. K. Chan, "Analysis of nonlinearities in MOS floating resistor networks," Proc. IEE Circuits, Devices, Syst., vol. 141, pp. 82-88, 1994.
15. T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate level weighted sum and threshold operations," IEEE Trans. Electron Devices, vol. 39, no. 10, pp. 1444-1455, Oct. 1992.
16. K. Nay and A. Budak, "A voltage-controlled resistance with wide dynamic range and low distortion," IEEE Trans. Circuit Syst., vol. CAS-30, no. 6, pp. 770-772, May 1983.
17. W. R. Patterson and F. S. Shoucair, "Harmonic suppression in unbalanced analogue MOSFET circuit topologies using body signals," Electron. Lett., vol. 25, pp. 1737-1739, 1989.
18. H. K. J. Ihantola and J. L. Moll, "Design theory of a surface field effect transistors," Solid-State Electron., vol. 7, pp. 423-430, 1964.
19. M. H. White, F. Van De Wiele, and J. P. Lambot, "High accuracy MOS models for computer-aided design," IEEE Trans. Electron Devices, vol. ED-27, no. 7, pp. 899-906, Jul. 1980.
20. Y. P. Tsividis, Operation and Modelling of the MOS Transistor. New York: McGraw-Hill, 1987.
21. H. Iizuka, F. Masuoka, T. Sato, and M. Ishikawa, "Electrically alterable avalanche-injection-type MOS read only memory with stacked-gate structure," IEEE Trans. Electron Devices, vol. ED-23, no. 3, pp. 379-387, Mar. 1976.
22. A. Bhattacharyya, "Modeling of write/erase and charge retention characteristics of floating gate EEPROM devices," Solid State Electron., vol. 27, pp. 899-906, 1984.
23. U. Feldmann, R. Kakoschke, M. Miura-Mattausch, and G. Schraud, "Concurrent technology, device, and circuit development for EEPROMs," in Proc. Asia South Pacific Design Autom. Conf., 1998, pp. 123-128.
24. R. Duane, M. F. Beug, and A. Mathewson, "Novel capacitance coupling coefficient measurement methodology for floating gate nonvolatile memory devices," IEEE Electron Device Lett., vol. 26, no. 3, pp. 507-509, Mar. 2005.
25. D. W. Graham, E. Farquhar, B. Degnan, C. Gordon, and P. E. Hasler, "Indirect programming of floating-gate transistors," in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 3, pp. 2172-2175.
26. C. Bleiker and H. Melchior, "A four-state EEPROM using floating-gate memory cell," IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 460-463, Mar. 1987.
27. Z. Czarnul and S. Tagaki, "Design of linear tunable CMOS differential transconductor cells," Electron. Lett., vol. 26, pp. 1809-1811, 1990.
28. A. Nedungadi and T. R. Viswanathan, "Design of linear CMOS transconductor elements," IEEE Trans. Circuits Syst., vol. CAS-31, no. 12, pp. 891-894, Dec. 1984.
29. Y. Sugimoto, "A 1-V operational, 20 MS/s and 57 dB of S/N, current-mode CMOS sample-and-hold IC," in Proc. Symp. VLSI Circuits, 2001, pp. 207-208.
30. Y. Sugimoto, "A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach," IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 51, no. 1, pp. 110-117, Jan. 2004.
31. S. D. Willingham, K. W. Martin, and A. Ganesan, "A BiCMOS low-distortion 8-MHz low-pass filter," IEEE J. Solid-State Circuits vol. 28, no. 6, pp. 1234-1245, Dec. 1993.
32. E. Özalevli, H. Dinc, H.-J. Lo, and P. E. Hasler, "Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors," in Proc. IEEE Custom Integr. Circuits Conf., 2006, pp. 149-152.
33. K. Vavelidis and Y. Tsividis, "R-MOSFET structure based on current division," Electron. Lett., vol. 29, pp. 732-733, 1993.
34. K. Vavelidis, Y. P. Tsividis, F. Op't Eynde, and Y. Papananos, "Six-terminal MOSFET's: Modelling and applications in highly linear, electronically tunable resistors," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 4-12, Jan. 1997.