![]() |
Volumn 51, Issue 1, 2004, Pages 110-117
|
A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach
a
CHUO UNIVERSITY
(Japan)
|
Author keywords
[No Author keywords available]
|
Indexed keywords
ANALOG TO DIGITAL CONVERSION;
ELECTRIC CURRENTS;
ELECTRIC POTENTIAL;
GATES (TRANSISTOR);
INTEGRATED CIRCUIT MANUFACTURE;
LSI CIRCUITS;
SIGNAL TO NOISE RATIO;
TRANSISTORS;
TRIODES;
CURRENT BASED CIRCUITS;
CURRENT TRANSFER RATIO;
SAMPLE-AND-HOLD IC;
SWITCHED CURRENT CIRCUIT;
CMOS INTEGRATED CIRCUITS;
|
EID: 4644315677
PISSN: 10577122
EISSN: None
Source Type: Journal
DOI: 10.1109/TCSI.2003.821295 Document Type: Article |
Times cited : (13)
|
References (10)
|