Flip-chip on flex integrated power electronics modules for high-density power integration

IEEE Transactions on Advanced Packaging

Volumn 26, Issue 1, 2003, Pages 54-59

  Bai, John G ^a,b   Lu, Guo Quan ^a,b   Liu, Xingsheng ^b,c  

^a State University   (United States)

^b VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^c NONE   (United States)

Author keywords

FCOF; Flip chip; HDMCM; IPEM; Power electronics packaging; Power module

Indexed keywords

FLIP CHIP DEVICES; MOSFET DEVICES; POWER ELECTRONICS; RELIABILITY; SOLDERED JOINTS; THERMAL STRESS;

ELECTRICAL CIRCUITS; GATE DRIVE CIRCUIT; SOLDER BUMPED DEVICES; THERMOMECHANICAL STRESSES;

ELECTRONICS PACKAGING;

EID: 0037942584     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2003.811367     Document Type: Article

References (18)

1. K. Xing, F. C. Lee, and D. Borojevic, "Extraction of parasitics within wire-bond IGBT modules," in Proc. Virginia Power Electron. Ctr. Sem., 1997, pp. 107-114.
2. T. Ericksen, A. Tucker, D. Hamilton, G. Campisi, C. Whitcomb, J. Borraccini, and W. Jacobson, "Standardized power switch system modules (power electronic building blocks)," in Proceedings of the PCIM Power Electronics Institute Power Semiconductor Specialists Course. New York: Power System World, 1997.
3. J. D. Van Wyk and F. C. Lee, "Power electronics technology-Status and future," in Proc. Virginia Power Electron. Ctr. Sem., 1999.
4. J. A. Ferreira, I. W. Hofsajer, and J. D. Van Wyk, "Exploiting the third dimension in power electronics packaging," in Proc. IEEE Appl. Power Electron. Conf., vol. 1, 1997, pp. 419-423.
5. R. Fisher, R. Fillion, J. Burgess, and W. Hennessy, "High frequency, low cost, power packaging using thin film power overlay technology," in Proc. IEEE Appl. Power Electron. Conf., May 1995, pp. 12-17.
6. Semikron International. New power connection and construction. Tech. Rep. [Online]. Available: http://www.semikron.com/jahr2000/skiip_techn.pdf.
7. R. W. Linden, L. Duncan, and R. Fryhoff, "Low cost integrated power module technology," in Proc. Power Electron.'98, 1998, pp. 130-140.
8. P. Mannion, "MOSFETs break out of the shackles of wirebonding," Electron. Design, p. 36, May 17, 1999.
9. A. Bindra, "Innovative packages maximize MOSFETs' thermal performance," Electron. Design, p. 52, May 17, 1999.
10. J. H. Lau, Flip Chip Technologies. New York: McGraw Hill, 1995.
11. R. R. Tummala, E. J. Rymaszewski, and A. G. Klopfenstein, Microelectronics Packaging Handbook. New York: Chapman & Hall, 1999.
12. M. Mueller, "Die attach: Step by step," Adv. Packag. Mag., p. 47, Mar. 2001.
13. J. N. Calata, G. Q. Lu, and C. Luechinger, "Evaluation of interconnection technologies for power semiconductor devices," in Proc. Ctr. Power Electron. Syst. Sem., 2002, pp. 96-105.
14. XYS Websites. [Online]. Available: http://www.ixys.com.
15. X. Liu, S. Xu, G.-Q. Lu, and D. A. Dillard, "Effect of substrate flexibility on solder joint reliability," Microelectron. Rel., vol. 42, pp. 1883-1891, 2002.
16. X. Liu, X. Jing, and G.-Q. Lu, "Chip-scale packaging of power devices and its application in integrated power electronics modules," IEEE Trans. Adv. Packag., vol. 24, pp. 206-215, May 2001.
17. Q. Yu, M. Shiratori, and Y. Ohshima, "A study of the effects of BGA solder geometry on fatigue and reliability assessment," in Proc. InterSoc. Conf. Thermal Phenom., 1998, pp. 229-235.
18. X. Liu, S. Xu, G.-Q. Lu, and D. A. Dillard, "Stacked solder bumping technology for improved solder joint reliability," Microelectron. Rel., vol. 41, pp. 1979-1992, 2001.