Low power encoding schemes for run-time on-chip bus

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 2, Issue , 2004, Pages 1025-1028

  Huang, Po Tsang ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; CROSSTALK; INTERCONNECTION NETWORKS; SIGNAL ENCODING; SPURIOUS SIGNAL NOISE;

COUPLING EFFECTS; DEEP SUB-MICRON (DSM); RUN TIME ON-CHIP BUS; SYSTEM ON CHIP (SOC) INTERCONNECTS;

MICROPROCESSOR CHIPS;

EID: 21644485957     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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