Power reduction in VLIW processor with compiler driven bypass network

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 233-238

  Goel, Neeraj ^a   Kumar, Anshul ^a   Panda, Preeti Ranjan ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BYPASS NETWORKS; CONTROL AREAS; CORE AREAS; ENERGY SAVINGS; ISSUE WIDTHS; MEDIA BENCHES; POWER REDUCTIONS; REGISTER FILES; SYNTHESIS OF; VLIW PROCESSORS;

COMPUTER PROGRAMMING LANGUAGES; INTEGRATED CIRCUITS; PORTS AND HARBORS; PROGRAM COMPILERS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EMBEDDED SYSTEMS;

EID: 44149099247     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.127     Document Type: Conference Paper

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