Systematic register bypass customization for application-specific processors

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2003-January, Issue , 2003, Pages 64-74

  Fan, Kevin ^a   Clark, Nathan ^a   Chu, Michael ^a   Manjunath, K V ^a   Ravindran, Rajiv ^a   Smelyanskiy, Mikhail ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVAILABILITY; COMPUTER ARCHITECTURE; COSTS; DESIGN; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PIPELINES; PROGRAM COMPILERS; SCHEDULING; SYSTEMS ANALYSIS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

APPLICATION SPECIFIC PROCESSORS; BYPASS NETWORKS; COMPILER SCHEDULING; GLOBAL INFORMATIONS; ITERATIVE DESIGN; PROCESSOR DESIGN; PROCESSOR PIPELINES; SYSTEMATIC DESIGNS;

PIPELINE PROCESSING SYSTEMS;

EID: 31644435575     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2003.1212830     Document Type: Conference Paper

References (21)

1. A. Abnous and N. Bagherzadeh. Pipelining and Bypassing in a VLIW processor. IEEE Transactions on Parallel and Distributed Systems, 5(6), June 1995.
2. S. Aditya, V. Kathail, and B. R. Rau. Elcor's Machine Description System: Version 3.0. Technical Report HPL-98-128, Hewlett-Packard Laboratories, Oct. 1998.
3. S. Aditya, B. R. Rau, and V. Kathail. Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors. In Proc. of ISSS, Nov. 1999.
4. P. Ahuja, D. Clark, and A. Rogers. The Performance Impact of Incomplete Bypassing in Processor Pipelines. In Proc. of Micro-28, Dec. 1995.
5. E. Bloch. The Engineering Design of the Stretch Computer. In Proc. of the Easter Joint Computer Gonf., 1959.
6. M. D. Brown and Y. Patt. Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. In Proc. of HPCA-8, Feb 2001.
7. M. Buss, R. Azevedo, P. Centoducatte, and G. Araujo. Tailoring Pipeline Bypassing and Functional Unit Mapping to Application in Clustered VLIW Architectures. In Proc. of CASES, Nov. 2001.
8. R. Cohn, T. Gross, M. Lam, and P. Tseng. Architecture and Compiler Tradeoffs for a Long Instrction Word Microprocessor. In Proc. of ASPLOS-3, April 1989.
9. J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985.
10. J. A. Fisher, P. Faraboschi, and G. Desoli. Custom-Fit Processors: Letting Applications Define Architectures. In Proc. of Micro-29, Dec 1996.
11. G. Hekstra et al. TriMedia CPU64 Design Space Exploration. In Proc. of ICCD, Oct. 1999.
12. I. Karkowski and H. Corporaal. Design Space Exploration Algorithm For Heterogeneous Multi-processor Embedded System Design. In Proc. of DAC-35, June 1998.
13. V. Lapinskii. Algorithms for Compiler-Assisted Design Space Exploration of Clustered VLIW ASIP Datapaths. PhD thesis, University of Texas, 2001.
14. C. Lee, M. Potkonjak, and W. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proc. of Micro-30, Dec. 1997.
15. P. Marwedel. The MIMOLA Design System: Tools for the Design of Digital Processors. In Proc of DAC-21, 1984.
16. E. McLellan. The Alpha AXP Architcture and 21064 processor. IEEE Micro, 13(3):36-47, June 1993.
17. S. Palacharla. Complexity-Effective Superscalar Processors. PhD thesis, Wisconsin, Madison, 1998.
18. J. Sato, M. Imai, T. Hakata, A. Alomary, and N. Hikichi. An Integrated Design Environment for Application Specific Integrated Processors. In Proc. of ICCD, Oct. 1991.
19. G. Snider. Spacewalker: Automated Design Space Exploration for Embedded Computer Systems. Technical Report HPL-2001-220, Hewlett-Packard Laboratories, Sept. 2001.
20. Trimaran. An Infrastructure for Research in ILP. http://www.trimaran.org.
21. L. Wu, C. Weaver, and T. Austin. Cryptomaniac: A Fast Flexible Architecture for Secure Communication. In Proc. of ISCA-28, June 2001.