A fast interrupt handling scheme for VLIW processors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1998, Pages 136-141

  Ozer, E ^a   Sathaye, S W ^a   Menezes, K N ^a   Banerjia, S ^a   Jennings, M D ^a   Conte, T M ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE; PARALLEL ARCHITECTURES;

COMPLEX HARDWARE; EMBEDDED PROCESSORS; INTERRUPT HANDLING; OUT-OF-ORDER EXECUTION; RE-ORDER BUFFERS; SEQUENTIAL STATE; SMALL BUFFERS; VLIW PROCESSOR;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84943180334     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.1998.727184     Document Type: Conference Paper

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