Low-power data forwarding for VLIW embedded architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 5, 2002, Pages 614-622

  Sami, Mariagiovanna ^a   Sciuto, Donatella ^a   Silvano, Cristina ^b   Zaccaria, Vittorio ^a   Zafalon, Roberto ^c  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF MILAN   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

Low power design; Microprocessors; VLSI design

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; SHIFT REGISTERS; VERY LONG INSTRUCTION WORD ARCHITECTURE; VLSI CIRCUITS;

COMPILER STATIC SCHEDULING ALGORITHM; EMBEDDED ARCHITECTURES; PIPELINE REGISTERS; PROCESSOR CONTROL LOGIC;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036819197     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.801617     Document Type: Article

References (17)

1. A. Chandrakasan and R. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, no. 4, pp. 498-523, 1995.
2. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley-Interscience, 2000.
3. L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, and R. Zafalon, "A power modeling and estimation framework for vliw-based embedded systems," in Proc. Int. Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS'01), Sept. 26-28, 2001.
4. V. Zyuban and P. Kogge, "The energy complexity of RF," in Proc. Int. Symp. Low-Power Electronic Design (ISLPED98), Monterey, CA, 1998, pp. 305-310.
5. J. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufmann, 1996.
6. H. Corporaal, Microprocessor Architectures: From VLIW to TTA. London, U.K.: Wiley, 1997.
7. A. Abnous and N. Bagherzadeh, "Pipelining and bypassing in a VLIW processor," IEEE Trans. Parallel Distrib. Syst., vol. 5, pp. 658-663, June 1994.
8. R. Yung and N. C. Wilhelm, "Caching processor general registers," in Proc. IEEE Int. Conf. Computer Design (ICCD'95), 1995, pp. 307-312.
9. L. A. Lozano and G. R. Gao, "Exploiting short-lived variables in superscalar processors," in Proc. 28th Annu. IEEE/ACM Int. Symp. Microarchitecture (MICRO-28), 1995, pp. 292-302.
10. M. M. Martin, A. Roth, and C. N. Fischer, "Exploiting dead value information," in Proc. 30th Annu. IEEE/ACM Int. Symp. Microarchitecture (MICRO-30), 1997, pp. 125-135.
11. P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homehood, "Lx: A technology platform for customizable VLIW embedded processing," in Proc. Int. Symp. Computer Architecture (ISCA'00), Vancouver, BC, Canada, 2000, pp. 203-213.
12. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon, "Exploiting data forwarding to reduce the power budget of VLIW embedded processors," in Design, Automation Test Europe 2001: Conf. Exhibition 2001 Proc., March 2001, pp. 252-257.
13. A. V. Aho, R. Sethi, and J. D. Ullman, Compilers: Principles, Techniques, and Tools. Reading, MA: Addison-Wesley, 1986.
14. J. Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE Trans. Comput., vol. C-30, pp. 478-490, July 1981.
15. J. K. Kin, M. Gupta, and W. H. Mangione-Smith, "Filtering memory references to increase energy efficiency," IEEE Trans. Comput., vol. 49, Jan. 2000.
16. W. H. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. Commun., vol. COM-25, pp. 1004-1009, Sept. 1977.
17. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C: The Art of Scientific Computing. Cambridge, U.K.: Cambridge Univ. Press, 1993.