FLASH: Foresighted latency-aware scheduling heuristic for processors with customized datapaths

International Symposium on Code Generation and Optimization, CGO

Volumn , Issue , 2004, Pages 201-212

  Kudlur, Manjunath ^a   Fan, Kevin ^a   Chu, Michael ^a   Ravindran, Rajiv ^a   Clark, Nathan ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUSTOMIZED DATAPATHS; EMBEDDED PROCESSORS; FUNCTIONAL UNITS (FU); LATENCY-AWARE SVHEDULING;

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER NETWORKS; EMBEDDED SYSTEMS; MULTIPROCESSING SYSTEMS; SCHEDULING;

PROGRAM PROCESSORS;

EID: 3042520990     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2004.1281675     Document Type: Conference Paper

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