A due-date-based algorithm for lot-order assignment in a semiconductor wafer fabrication facility

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 2, 2008, Pages 209-215

  Kim, Yeong Dae ^a,b   Bang, June Young ^b   An, Kwee Yeon ^c   Lim, Seung Kil ^d  

^a IEEE

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c SAMSUNG Electronics   (South Korea)

^d Sungkyul University   (South Korea)

Author keywords

Lot order assignment; Scheduling; Semiconductor wafer fab

Indexed keywords

COMPUTER SIMULATION; DATA REDUCTION; PROBLEM SOLVING; SEMICONDUCTOR MATERIALS; WAFER BONDING;

LOT-ORDER ASSIGNMENT; PEGGING PROBLEM; SEMICONDUCTOR WAFER FAB;

ALGORITHMS;

EID: 43849105260     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2008.2000261     Document Type: Conference Paper

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