메뉴 건너뛰기




Volumn 17, Issue 5, 2001, Pages 589-598

Production scheduling in a semiconductor wafer fabrication facility producing multiple product types with distinct due dates

Author keywords

Batch scheduling; Lot release control; Lot scheduling; Semiconductor wafer fabrication; Simulation; Tardiness

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; DECISION MAKING; MACHINERY; PROCESS CONTROL; PRODUCTION CONTROL; SCHEDULING; STATISTICAL METHODS;

EID: 0035485317     PISSN: 1042296X     EISSN: None     Source Type: Journal    
DOI: 10.1109/70.964660     Document Type: Article
Times cited : (90)

References (23)
  • 9
    • 0027842088 scopus 로고    scopus 로고
    • Practical issues in scheduling and dispatching in semiconductor wafer fabrication
    • (1998) J. Manufact. Syst. , vol.12 , pp. 474-485
    • Johri, P.K.1
  • 16
    • 0032003105 scopus 로고    scopus 로고
    • Minimizing total tardiness on a batch processing machine with incompatible job families
    • (1998) IIE Trans. , vol.30 , pp. 165-178
    • Sanjay, V.M.1    Uzsoy, R.2
  • 18
    • 0025430088 scopus 로고
    • A comparison of dispatching rules for job shops with multiple identical jobs and alternative routeings
    • (1990) Int. J. Prod. Res. , vol.28 , pp. 953-962
    • Kim, Y.-D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.