A parameterized-dispatching rule for a Logic IC sort in a wafer fabrication

Production Planning and Control

Volumn 16, Issue 5, 2005, Pages 426-436

  Lin, J T ^a   Wang, F K ^b   Kuo, P C ^a,c  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^c National Tsing Hua University ^*

Author keywords

IC sort; Multi attributes; Multiple performance measures; Parameterized dispatching rule

Indexed keywords

COMPUTER SIMULATION; LOGIC CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; PRODUCT DESIGN;

IC SORT; MULTI-ATTRIBUTES; PARAMETERIZED DISPATCHING RULE;

INTEGRATED CIRCUITS;

EID: 32144432329     PISSN: 09537287     EISSN: 13665871     Source Type: Journal    
DOI: 10.1080/09537280500110623     Document Type: Article

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