Automated design space exploration of FPGA-based FFT architectures based on area and power estimation

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Volumn , Issue , 2006, Pages 127-134

  Sanchez M A ^a   Garrido, M ^a   Vallejo, M López ^a   Lopez Barrio C ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

FAST FOURIER TRANSFORMS; PARAMETER ESTIMATION; USER INTERFACES;

AUTOMATED DESIGN SPACE EXPLORATION; DESIGN SPACE; PIPELINED ARCHITECTURES; POWER ESTIMATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43749106474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270303     Document Type: Conference Paper

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