Digital channelised receivers on FPGAs platforms

IEEE National Radar Conference - Proceedings

Volumn 2005-January, Issue January, 2005, Pages 816-821

  Sánchez, Miguel Angel ^a   Garrido, Mario ^a   López Vallejo, Marisa ^b   Grajal, Jesus ^c   López Barrio, Carlos ^a  

^a Dep Ingenieria Electrónica   (Spain)

^b Dep Senales Sistemas   (Spain)

^c UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

Channelised receiver; FFT; FPGA; Monobit FFT; parallel architectures; STFT

Indexed keywords

ELECTRONIC WARFARE; FAST FOURIER TRANSFORMS; INTERFERENCE SUPPRESSION; PARALLEL ARCHITECTURES; RADAR; SIGNAL RECEIVERS;

DIGITAL RECEIVERS; FFT ALGORITHM; NONSTATIONARY SIGNALS; REAL TIME; SHORT TIME FOURIER TRANSFORMS; SPEED PROCESSING; STFT; TIME FREQUENCY ANALYSIS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 40949089192     PISSN: 10975659     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RADAR.2005.1435939     Document Type: Conference Paper

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